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ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x
authorPeter Ujfalusi <peter.ujfalusi@ti.com>
Thu, 12 Mar 2015 08:06:30 +0000 (10:06 +0200)
committerSekhar Nori <nsekhar@ti.com>
Wed, 18 Mar 2015 11:47:36 +0000 (17:17 +0530)
McASP1 TX interrupt is 30, not 32 on DM646x DMSoC.

While at it remove the bogus AEMIF interrupt entry from
dm646x_default_priorities[]. AEMIF interrupt on DM6467 is
60 not 30 and the entry for the correct interrupt number
is already present in the same table.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: remove bogus entry from dm646x_default_priorities[]]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arch/arm/mach-davinci/dm646x.c patch | blob | history
arch/arm/mach-davinci/include/mach/irqs.h patch | blob | history

diff --cc arch/arm/mach-davinci/dm646x.c
Simple merge
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