Fix PHYTEC EEPROM bus mismatch between SPL and U-Boot proper by enabling
CONFIG_SPL_DM_SEQ_ALIAS=y on phyCORE-i.MX93 boards. This way, both the
SPL and U-Boot proper will respect the device-tree aliases for I2C devs
and use the same I2C bus number for phytec_eeprom_data_setup() function
calls. This makes code less confusing and more robust.
Fixes an issue apparent since commit
79f3e77133bd ("Subtree merge tag
'v6.16-dts' of dts repo [1] into dts/upstream") where SPL would spew the
following error:
phytec_eeprom_read: i2c EEPROM not found: -110.
phytec_eeprom_data_setup: EEPROM data init failed
While later in U-Boot proper, EEPROM would be successfully read out.
This happens because Linux device-tree for phyBOARD-Segin-i.MX93 since
aforementioned commit enables I2C bus 2 (lpi2c2 is used for audio codec
and RTC) which breaks SPL I2C bus number ordering and I2C EEPROM bus is
shifted by +1. Now, lets prevent this from happening again by utilizing
device-tree aliases also in the SPL.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
int ret;
enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID;
- /* NOTE: In SPL lpi2c3 is mapped to bus 0 */
- ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
+ ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
goto out;
CONFIG_ETHPRIME="eth1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_CLK_IMX93=y
CONFIG_CLK_IMX93=y
CONFIG_DFU_MMC=y