drm/i915: Explain why we need to write DPLL twice

... it's because setting the Pixel Multiply bits only takes effect once
the PLL is enabled and stable.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f7962b7..e3b8d0d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4089,13 +4089,13 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                        }
                        I915_WRITE(DPLL_MD(pipe), temp);
                } else {
-                       /* write it again -- the BIOS does, after all */
+                       /* The pixel multiplier can only be updated once the
+                        * DPLL is enabled and the clocks are stable.
+                        *
+                        * So write it again.
+                        */
                        I915_WRITE(dpll_reg, dpll);
                }
-
-               /* Wait for the clocks to stabilize. */
-               POSTING_READ(dpll_reg);
-               udelay(150);
        }
 
        intel_crtc->lowfreq_avail = false;