source "board/imgtec/boston/Kconfig"
source "board/imgtec/malta/Kconfig"
source "board/imgtec/xilfpga/Kconfig"
-source "board/micronas/vct/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-mscc/Kconfig"
char *old_str;
char *new_str;
} reg_names_map[] = {
- { "ccsr", "dip" },
+ { "ccsr", "dbi" },
{ "pf_ctrl", "ctrl" }
};
int off = -1, i;
+++ /dev/null
-if TARGET_VCT
-
-config SYS_BOARD
- default "vct"
-
-config SYS_VENDOR
- default "micronas"
-
-config SYS_CONFIG_NAME
- default "vct"
-
-config SYS_TEXT_BASE
- default 0x87000000
-
-config SYS_DCACHE_SIZE
- default 16384
-
-config SYS_DCACHE_LINE_SIZE
- default 32
-
-config SYS_ICACHE_SIZE
- default 16384
-
-config SYS_ICACHE_LINE_SIZE
- default 32
-
-menu "vct board options"
-
-choice
- prompt "Board variant"
- optional
-
-config VCT_PLATINUM
- bool "Enable VCT_PLATINUM"
-
-config VCT_PLATINUMAVC
- bool "Enable VCT_PLATINUMAVC"
-
-config VCT_PREMIUM
- bool "Enable VCT_PLATINUMAVC"
-
-endchoice
-
-config VCT_ONENAND
- bool "Enable VCT_ONENAND"
-
-config VCT_SMALL_IMAGE
- bool "Enable VCT_SMALL_IMAGE"
-
-endmenu
-
-endif
+++ /dev/null
-VCT BOARD
-#M: -
-S: Maintained
-F: board/micronas/vct/
-F: include/configs/vct.h
-F: configs/vct_platinum_defconfig
-F: configs/vct_platinum_onenand_defconfig
-F: configs/vct_platinum_onenand_small_defconfig
-F: configs/vct_platinum_small_defconfig
-F: configs/vct_platinumavc_defconfig
-F: configs/vct_platinumavc_onenand_defconfig
-F: configs/vct_platinumavc_onenand_small_defconfig
-F: configs/vct_platinumavc_small_defconfig
-F: configs/vct_premium_defconfig
-F: configs/vct_premium_onenand_defconfig
-F: configs/vct_premium_onenand_small_defconfig
-F: configs/vct_premium_small_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
-
-obj-y := vct.o
-obj-y += ebi.o
-obj-$(CONFIG_VCT_NOR) += ebi_nor_flash.o
-obj-$(CONFIG_VCT_ONENAND) += ebi_onenand.o
-obj-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o
-obj-y += gpio.o
-obj-y += top.o
-obj-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#ifndef _BCU_H
-#define _BCU_H
-
-enum bcu_tags {
- BCU_VBV1 = 0,
- BCU_VBV2 = 1,
- BCU_BSS1 = 2,
- BCU_BSS2 = 3,
- BCU_TSD_TXT = 4,
- BCU_TSD_SUBTITLES = 5,
- BCU_TSD_PES_0 = 6,
- BCU_TSD_PES_1 = 7,
- BCU_TSD_PES_2 = 8,
- BCU_TSD_PES_3 = 9,
- BCU_TSIO_RECORD_0 = 10,
- BCU_TSIO_RECORD_1 = 11,
- BCU_TSIO_PLAYBACK_0 = 12,
- BCU_TSIO_PLAYBACK_1 = 13,
- BCU_SECURE_BUFFER = 14,
- BCU_PCM1 = 15,
- BCU_PCM2 = 16,
- BCU_BSS_COPY = 17,
- BCU_BSS_EXT1 = 18,
- BCU_BSS_EXT2 = 19,
- BCU_PCM_JINGLE = 20,
- BCU_EBI_CPU_BUFFER = 21,
- BCU_PCM_DELAY = 22,
- BCU_FH_BUFFER_0 = 23,
- BCU_FH_BUFFER_1 = 24,
- BCU_TSD_SECTION_0 = 25,
- BCU_TSD_SECTION_1 = 26,
- BCU_TSD_SECTION_2 = 27,
- BCU_TSD_SECTION_3 = 28,
- BCU_TSD_SECTION_4 = 29,
- BCU_TSD_SECTION_5 = 30,
- BCU_TSD_SECTION_6 = 31,
- BCU_TSD_SECTION_7 = 32,
- BCU_TSD_SECTION_8 = 33,
- BCU_TSD_SECTION_9 = 34,
- BCU_TSD_SECTION_10 = 35,
- BCU_TSD_SECTION_11 = 36,
- BCU_TSD_SECTION_12 = 37,
- BCU_TSD_SECTION_13 = 38,
- BCU_TSD_SECTION_14 = 39,
- BCU_TSD_SECTION_15 = 40,
- BCU_TSD_SECTION_16 = 41,
- BCU_TSD_SECTION_17 = 42,
- BCU_TSD_SECTION_18 = 43,
- BCU_TSD_SECTION_19 = 44,
- BCU_TSD_SECTION_20 = 45,
- BCU_TSD_SECTION_21 = 46,
- BCU_TSD_SECTION_22 = 47,
- BCU_TSD_SECTION_23 = 48,
- BCU_TSD_SECTION_24 = 49,
- BCU_TSD_SECTION_25 = 50,
- BCU_TSD_SECTION_26 = 51,
- BCU_TSD_SECTION_27 = 52,
- BCU_TSD_SECTION_28 = 53,
- BCU_TSD_SECTION_29 = 54,
- BCU_TSD_SECTION_30 = 55,
- BCU_TSD_SECTION_31 = 56,
- BCU_TSD_SECTION_32 = 57,
- BCU_TSD_SECTION_33 = 58,
- BCU_TSD_SECTION_34 = 59,
- BCU_TSD_SECTION_35 = 60,
- BCU_TSD_SECTION_36 = 61,
- BCU_TSD_SECTION_37 = 62,
- BCU_TSD_SECTION_38 = 63,
- BCU_TSD_SECTION_39 = 64,
- BCU_TSD_SECTION_40 = 65,
- BCU_TSD_SECTION_41 = 66,
- BCU_TSD_SECTION_42 = 67,
- BCU_TSD_SECTION_43 = 68,
- BCU_TSD_SECTION_44 = 69,
- BCU_TSD_SECTION_45 = 70,
- BCU_TSD_SECTION_46 = 71,
- BCU_TSD_SECTION_47 = 72,
- BCU_TSD_SECTION_48 = 73,
- BCU_TSD_SECTION_49 = 74,
- BCU_TSD_SECTION_50 = 75,
- BCU_TSD_SECTION_51 = 76,
- BCU_TSD_SECTION_52 = 77,
- BCU_TSD_SECTION_53 = 78,
- BCU_TSIO_RECORD_2 = 79,
- BCU_TSIO_RECORD_3 = 80,
- BCU_TSIO_RECORD_4 = 81,
- BCU_TSIO_RECORD_5 = 82,
- BCU_TSIO_RECORD_6 = 83,
- BCU_TSIO_RECORD_7 = 84,
- BCU_TSIO_RECORD_8 = 85,
- BCU_TSIO_RECORD_9 = 86,
- BCU_PCM_DELAY_LINEAR = 87,
- BCU_VD_MASTER_USER_DATA = 88,
- BCU_VD_SLAVE_USER_DATA = 89,
- BCU_VD_MASTER_REF0 = 90,
- BCU_VD_MASTER_REF1 = 91,
- BCU_VD_SLAVE_REF0 = 92,
- BCU_VD_SLAVE_REF1 = 93,
- BCU_VD_MASTER_DISP0_Y = 94,
- BCU_VD_MASTER_DISP1_Y = 95,
- BCU_VD_MASTER_DISP2_Y = 96,
- BCU_VD_MASTER_DISP0_C = 97,
- BCU_VD_MASTER_DISP1_C = 98,
- BCU_VD_MASTER_DISP2_C = 99,
- BCU_VD_SLAVE_DISP0_Y = 100,
- BCU_VD_SLAVE_DISP1_Y = 101,
- BCU_VD_SLAVE_DISP2_Y = 102,
- BCU_VD_SLAVE_DISP0_C = 103,
- BCU_VD_SLAVE_DISP1_C = 104,
- BCU_VD_SLAVE_DISP2_C = 105,
- BCU_CLUT_BUFFER_0 = 106,
- BCU_CLUT_BUFFER_1 = 107,
- BCU_OSD_FRAME_BUFFER_0 = 108,
- BCU_OSD_FRAME_BUFFER_1 = 109,
- BCU_GRAPHIC_FRAME_BUFFER0 = 110,
- BCU_GRAPHIC_FRAME_BUFFER1 = 111,
- BCU_DVP_VBI_REINSERTION = 112,
- BCU_DVP_OSD_FRAME_BUFFER0 = 113,
- BCU_DVP_OSD_FRAME_BUFFER1 = 114,
- BCU_GAI_BUFFER = 115,
- BCU_GA_SRC_BUFFER_0 = 116,
- BCU_GA_SRC_BUFFER_1 = 117,
- BCU_USB_BUFFER_0 = 118,
- BCU_USB_BUFFER_1 = 119,
- BCU_FE_3DCOMB_0 = 120,
- BCU_FE_3DCOMB_1 = 121,
- BCU_FE_3DCOMB_2 = 122,
- BCU_FE_3DCOMB_3 = 123,
- BCU_TNR_BUFFER_0 = 124,
- BCU_TNR_BUFFER_1 = 125,
- BCU_TNR_BUFFER_2 = 126,
- BCU_MVAL_BUFFER = 127,
- BCU_RC_BUFFER_0 = 128,
- BCU_RC_BUFFER_1 = 129,
- BCU_RC_BUFFER_2 = 130,
- BCU_RC_BUFFER_3 = 131,
- BCU_PIP_BUFFER_0 = 132,
- BCU_PIP_BUFFER_1 = 133,
- BCU_PIP_BUFFER_2 = 134,
- BCU_PIP_BUFFER_3 = 135,
- BCU_EWARP_BUFFER = 136,
- BCU_OSD_BUFFER_0 = 137,
- BCU_OSD_BUFFER_1 = 138,
- BCU_GLOBAL_BUFFER_0 = 139,
- BCU_GLOBAL_BUFFER_1 = 140,
- BCU_MAX = 141
-};
-
-#endif /* _BCU_H */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Original Author Guenter Gebhardt
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#include <common.h>
-#include <linux/errno.h>
-
-#include "vct.h"
-
-int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
-{
- u32 enable;
- union dcgu_clk_en1 en1;
- union dcgu_clk_en2 en2;
-
- switch (setup) {
- case DCGU_SWITCH_ON:
- enable = 1;
- break;
- case DCGU_SWITCH_OFF:
- enable = 0;
- break;
- default:
- printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__,
- setup);
- return -EINVAL;
- }
-
- if (module == DCGU_HW_MODULE_CPU)
- en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
- else
- en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
-
- switch (module) {
- case DCGU_HW_MODULE_MSMC:
- en1.bits.en_clkmsmc = enable;
- break;
- case DCGU_HW_MODULE_SSI_S:
- en1.bits.en_clkssi_s = enable;
- break;
- case DCGU_HW_MODULE_SSI_M:
- en1.bits.en_clkssi_m = enable;
- break;
- case DCGU_HW_MODULE_SMC:
- en1.bits.en_clksmc = enable;
- break;
- case DCGU_HW_MODULE_EBI:
- en1.bits.en_clkebi = enable;
- break;
- case DCGU_HW_MODULE_USB_PLL:
- en1.bits.en_usbpll = enable;
- break;
- case DCGU_HW_MODULE_USB_60:
- en1.bits.en_clkusb60 = enable;
- break;
- case DCGU_HW_MODULE_USB_24:
- en1.bits.en_clkusb24 = enable;
- break;
- case DCGU_HW_MODULE_UART_2:
- en1.bits.en_clkuart2 = enable;
- break;
- case DCGU_HW_MODULE_UART_1:
- en1.bits.en_clkuart1 = enable;
- break;
- case DCGU_HW_MODULE_PERI:
- en1.bits.en_clkperi20 = enable;
- break;
- case DCGU_HW_MODULE_CPU:
- en2.bits.en_clkcpu = enable;
- break;
- case DCGU_HW_MODULE_I2S:
- en1.bits.en_clk_i2s_dly = enable;
- break;
- case DCGU_HW_MODULE_ABP_SCC:
- en1.bits.en_clk_scc_abp = enable;
- break;
- case DCGU_HW_MODULE_SPDIF:
- en1.bits.en_clk_dtv_spdo = enable;
- break;
- case DCGU_HW_MODULE_AD:
- en1.bits.en_clkad = enable;
- break;
- case DCGU_HW_MODULE_MVD:
- en1.bits.en_clkmvd = enable;
- break;
- case DCGU_HW_MODULE_TSD:
- en1.bits.en_clktsd = enable;
- break;
- case DCGU_HW_MODULE_GA:
- en1.bits.en_clkga = enable;
- break;
- case DCGU_HW_MODULE_DVP:
- en1.bits.en_clkdvp = enable;
- break;
- case DCGU_HW_MODULE_MR2:
- en1.bits.en_clkmr2 = enable;
- break;
- case DCGU_HW_MODULE_MR1:
- en1.bits.en_clkmr1 = enable;
- break;
- default:
- printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
- __LINE__, module);
- return -EINVAL;
- }
-
- /*
- * The reg_read() following the reg_write() below forces the write to
- * be really done on the bus.
- * Otherwise the clock may not be switched on when this API function
- * returns, which may cause an bus error if a registers of the hardware
- * module connected to the clock is accessed.
- */
- if (module == DCGU_HW_MODULE_CPU) {
- reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg);
- en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
- } else {
- reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg);
- en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
- }
-
- return 0;
-}
-
-int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
-{
- union dcgu_reset_unit1 val;
- u32 enable;
-
- switch (setup) {
- case DCGU_SWITCH_ON:
- enable = 1;
- break;
- case DCGU_SWITCH_OFF:
- enable = 0;
- break;
- default:
- printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__,
- setup);
- return -EINVAL;
- }
-
- val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE));
- switch (module) {
- case DCGU_HW_MODULE_MSMC:
- val.bits.swreset_clkmsmc = enable;
- break;
- case DCGU_HW_MODULE_SSI_S:
- val.bits.swreset_clkssi_s = enable;
- break;
- case DCGU_HW_MODULE_SSI_M:
- val.bits.swreset_clkssi_m = enable;
- break;
- case DCGU_HW_MODULE_SMC:
- val.bits.swreset_clksmc = enable;
- break;
- case DCGU_HW_MODULE_EBI:
- val.bits.swreset_clkebi = enable;
- break;
- case DCGU_HW_MODULE_USB_60:
- val.bits.swreset_clkusb60 = enable;
- break;
- case DCGU_HW_MODULE_USB_24:
- val.bits.swreset_clkusb24 = enable;
- break;
- case DCGU_HW_MODULE_UART_2:
- val.bits.swreset_clkuart2 = enable;
- break;
- case DCGU_HW_MODULE_UART_1:
- val.bits.swreset_clkuart1 = enable;
- break;
- case DCGU_HW_MODULE_PWM:
- val.bits.swreset_pwm = enable;
- break;
- case DCGU_HW_MODULE_GPT:
- val.bits.swreset_gpt = enable;
- break;
- case DCGU_HW_MODULE_I2C2:
- val.bits.swreset_i2c2 = enable;
- break;
- case DCGU_HW_MODULE_I2C1:
- val.bits.swreset_i2c1 = enable;
- break;
- case DCGU_HW_MODULE_GPIO2:
- val.bits.swreset_gpio2 = enable;
- break;
- case DCGU_HW_MODULE_GPIO1:
- val.bits.swreset_gpio1 = enable;
- break;
- case DCGU_HW_MODULE_CPU:
- val.bits.swreset_clkcpu = enable;
- break;
- case DCGU_HW_MODULE_I2S:
- val.bits.swreset_clk_i2s_dly = enable;
- break;
- case DCGU_HW_MODULE_ABP_SCC:
- val.bits.swreset_clk_scc_abp = enable;
- break;
- case DCGU_HW_MODULE_SPDIF:
- val.bits.swreset_clk_dtv_spdo = enable;
- break;
- case DCGU_HW_MODULE_AD:
- val.bits.swreset_clkad = enable;
- break;
- case DCGU_HW_MODULE_MVD:
- val.bits.swreset_clkmvd = enable;
- break;
- case DCGU_HW_MODULE_TSD:
- val.bits.swreset_clktsd = enable;
- break;
- case DCGU_HW_MODULE_TSIO:
- val.bits.swreset_clktsio = enable;
- break;
- case DCGU_HW_MODULE_GA:
- val.bits.swreset_clkga = enable;
- break;
- case DCGU_HW_MODULE_MPC:
- val.bits.swreset_clkmpc = enable;
- break;
- case DCGU_HW_MODULE_CVE:
- val.bits.swreset_clkcve = enable;
- break;
- case DCGU_HW_MODULE_DVP:
- val.bits.swreset_clkdvp = enable;
- break;
- case DCGU_HW_MODULE_MR2:
- val.bits.swreset_clkmr2 = enable;
- break;
- case DCGU_HW_MODULE_MR1:
- val.bits.swreset_clkmr1 = enable;
- break;
- default:
- printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
- __LINE__, module);
- return -EINVAL;
- }
- reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg);
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#ifndef _DCGU_H
-#define _DCGU_H
-
-enum dcgu_switch {
- DCGU_SWITCH_OFF, /* Switch off */
- DCGU_SWITCH_ON /* Switch on */
-};
-
-enum dcgu_hw_module {
- DCGU_HW_MODULE_DCGU, /* Selects digital clock gen. unit */
-
- DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface */
- DCGU_HW_MODULE_SCI, /* Selects SCI target agent port modules*/
-
- DCGU_HW_MODULE_MR1, /* Selects first MPEG reader module */
- DCGU_HW_MODULE_MR2, /* Selects second MPEG reader module */
- DCGU_HW_MODULE_MVD, /* Selects MPEG video decoder module */
- DCGU_HW_MODULE_DVP, /* Selects dig video processing module */
- DCGU_HW_MODULE_CVE, /* Selects color video encoder module */
- DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module */
-
- DCGU_HW_MODULE_SSI_S, /* Selects slave sync serial interface */
- DCGU_HW_MODULE_SSI_M, /* Selects master sync serial interface */
-
- DCGU_HW_MODULE_GA, /* Selects graphics accelerator module */
- DCGU_HW_MODULE_DGPU, /* Selects digital graphics processing */
-
- DCGU_HW_MODULE_UART_1, /* Selects first UART module */
- DCGU_HW_MODULE_UART_2, /* Selects second UART module */
-
- DCGU_HW_MODULE_AD, /* Selects audio decoder module */
- DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing */
- DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/
- DCGU_HW_MODULE_SPDIF, /* Selects sony philips digital interf. */
-
- DCGU_HW_MODULE_TSIO, /* Selects trasnport stream input/output*/
- DCGU_HW_MODULE_TSD, /* Selects trasnport stream decoder */
- DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */
-
- DCGU_HW_MODULE_USBH, /* Selects USB hub module */
- DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */
- DCGU_HW_MODULE_USB_60, /* Selects USB 60 module */
- DCGU_HW_MODULE_USB_24, /* Selects USB 24 module */
-
- DCGU_HW_MODULE_PERI, /* Selects all mod connected to clkperi20*/
- DCGU_HW_MODULE_WDT, /* Selects wtg timer mod con to clkperi20*/
- DCGU_HW_MODULE_I2C1, /* Selects first I2C mod con to clkperi20*/
- DCGU_HW_MODULE_I2C2, /* Selects 2nd I2C mod con to clkperi20 */
- DCGU_HW_MODULE_GPIO1, /* Selects gpio module 1 */
- DCGU_HW_MODULE_GPIO2, /* Selects gpio module 2 */
-
- DCGU_HW_MODULE_GPT, /* Selects gpt mod connected to clkperi20*/
- DCGU_HW_MODULE_PWM, /* Selects pwm mod connected to clkperi20*/
-
- DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */
- DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */
-
- DCGU_HW_MODULE_COM, /* Selects COM unit module */
- DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */
- DCGU_HW_MODULE_FWSRAM, /* Selects firmware SRAM module */
-
- DCGU_HW_MODULE_EBI, /* Selects external bus interface module*/
- DCGU_HW_MODULE_I2S, /* Selects integrated interchip sound */
- DCGU_HW_MODULE_MSMC, /* Selects memory stick and mmc module */
- DCGU_HW_MODULE_SMC, /* Selects smartcard interface module */
-
- DCGU_HW_MODULE_IRQC, /* Selects interrupt C module */
- DCGU_HW_MODULE_TOP, /* Selects top level pinmux module */
- DCGU_HW_MODULE_SRAM, /* Selects SRAM module */
- DCGU_HW_MODULE_EIC, /* Selects External Interrupt controller*/
- DCGU_HW_MODULE_CPU, /* Selects CPU subsystem module */
- DCGU_HW_MODULE_SCC, /* Selects SCC module */
- DCGU_HW_MODULE_MM, /* Selects Memory Manager module */
- DCGU_HW_MODULE_BCU, /* Selects Buffer Configuration Unit */
- DCGU_HW_MODULE_FH, /* Selects FIFO Handler module */
- DCGU_HW_MODULE_IMU, /* Selects Interrupt Management Unit */
- DCGU_HW_MODULE_MDU, /* Selects MCI Debug Unit module */
- DCGU_HW_MODULE_SI2OCP /* Selects Standard Interface to OCP bridge*/
-};
-
-union dcgu_clk_en1 {
- u32 reg;
- struct {
- u32 res1:8; /* reserved */
- u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */
- u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */
- u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */
- u32 en_clksmc:1; /* Enable bit for clksmc (#) */
- u32 en_clkebi:1; /* Enable bit for clkebi (#) */
- u32 en_usbpll:1; /* Enable bit for the USB PLL */
- u32 en_clkusb60:1; /* Enable bit for clkusb60 (#) */
- u32 en_clkusb24:1; /* Enable bit for clkusb24 (#) */
- u32 en_clkuart2:1; /* Enable bit for clkuart2 (#) */
- u32 en_clkuart1:1; /* Enable bit for clkuart1 (#) */
- u32 en_clkperi20:1; /* Enable bit for clkperi20 (#) */
- u32 res2:3; /* reserved */
- u32 en_clk_i2s_dly:1; /* Enable bit for clk_scc_abp */
- u32 en_clk_scc_abp:1; /* Enable bit for clk_scc_abp */
- u32 en_clk_dtv_spdo:1; /* Enable bit for clk_dtv_spdo */
- u32 en_clkad:1; /* Enable bit for clkad (#) */
- u32 en_clkmvd:1; /* Enable bit for clkmvd (#) */
- u32 en_clktsd:1; /* Enable bit for clktsd (#) */
- u32 en_clkga:1; /* Enable bit for clkga (#) */
- u32 en_clkdvp:1; /* Enable bit for clkdvp (#) */
- u32 en_clkmr2:1; /* Enable bit for clkmr2 (#) */
- u32 en_clkmr1:1; /* Enable bit for clkmr1 (#) */
- } bits;
-};
-
-union dcgu_clk_en2 {
- u32 reg;
- struct {
- u32 res1:31; /* reserved */
- u32 en_clkcpu:1; /* Enable bit for clkcpu */
- } bits;
-};
-
-union dcgu_reset_unit1 {
- u32 reg;
- struct {
- u32 res1:1;
- u32 swreset_clkmsmc:1;
- u32 swreset_clkssi_s:1;
- u32 swreset_clkssi_m:1;
- u32 swreset_clksmc:1;
- u32 swreset_clkebi:1;
- u32 swreset_clkusb60:1;
- u32 swreset_clkusb24:1;
- u32 swreset_clkuart2:1;
- u32 swreset_clkuart1:1;
- u32 swreset_pwm:1;
- u32 swreset_gpt:1;
- u32 swreset_i2c2:1;
- u32 swreset_i2c1:1;
- u32 swreset_gpio2:1;
- u32 swreset_gpio1:1;
- u32 swreset_clkcpu:1;
- u32 res2:2;
- u32 swreset_clk_i2s_dly:1;
- u32 swreset_clk_scc_abp:1;
- u32 swreset_clk_dtv_spdo:1;
- u32 swreset_clkad:1;
- u32 swreset_clkmvd:1;
- u32 swreset_clktsd:1;
- u32 swreset_clktsio:1;
- u32 swreset_clkga:1;
- u32 swreset_clkmpc:1;
- u32 swreset_clkcve:1;
- u32 swreset_clkdvp:1;
- u32 swreset_clkmr2:1;
- u32 swreset_clkmr1:1;
- } bits;
-};
-
-int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
-int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
-
-#endif /* _DCGU_H */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include "vct.h"
-
-int ebi_initialize(void)
-{
-#if defined(CONFIG_VCT_NOR)
- if (ebi_init_nor_flash())
- return -1;
-#endif
-
-#if defined(CONFIG_VCT_ONENAND)
- if (ebi_init_onenand())
- return -1;
-#endif
-
-#if defined(CONFIG_DRIVER_SMC911X)
- if (ebi_init_smc911x())
- return -1;
-#endif
-
- reg_write(EBI_CTRL_SIG_ACTLV(EBI_BASE), 0x00004100);
-
- ebi_wait();
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#ifndef __EBI__
-#define __EBI__
-
-#include <common.h>
-#include <asm/io.h>
-#include "vct.h"
-
-#define EXT_DEVICE_CHANNEL_3 (0x30000000)
-#define EXT_DEVICE_CHANNEL_2 (0x20000000)
-#define EXT_DEVICE_CHANNEL_1 (0x10000000)
-#define EXT_CPU_ACCESS_ACTIVE (0x00000001)
-#define EXT_DMA_ACCESS_ACTIVE (1 << 14)
-#define EXT_CPU_IORDY_SL (0x00000001)
-
-#define EBI_CPU_WRITE (1 << 31)
-#define EBI_CPU_ID_SHIFT (28)
-#define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT)
-
-/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */
-#define ADDR_LATCH_ENABLE 0
-#define ADDR_ACTIVATION 4
-#define CHIP_SELECT_START 8
-#define OUTPUT_ENABLE_START 12
-#define WAIT_TIME 28
-#define READ_DURATION 20
-
-/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */
-#define OUTPUT_ENABLE_END 0
-#define CHIP_SELECT_END 4
-#define ADDR_DEACTIVATION 8
-#define RECOVER_TIME 12
-#define ACK_TIME 20
-
-/* various bits in configuration register EBI_DEV[01]_CONFIG1 */
-#define EBI_EXTERNAL_DATA_8 (1 << 8)
-#define EBI_EXT_ADDR_SHIFT (1 << 22)
-#define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT
-#define EBI_CHIP_SELECT_1 0x2
-#define EBI_CHIP_SELECT_2 0x4
-#define EBI_BUSY_EN_RD (1 << 12)
-#define DIR_ACCESS_WRITE (1 << 20)
-#define DIR_ACCESS_MASK (1 << 20)
-
-/* various bits in configuration register EBI_DEV[01]_CONFIG2 */
-#define ADDRESS_INCREMENT_ON 0x0
-#define ADDRESS_INCREMENT_OFF 0x100
-#define QUEUE_LENGTH_1 0x40
-#define QUEUE_LENGTH_2 0x80
-#define QUEUE_LENGTH_3 0xC0
-#define QUEUE_LENGTH_4 0
-#define CPU_TRANSFER_SIZE_32 0
-#define CPU_TRANSFER_SIZE_16 0x10
-#define CPU_TRANSFER_SIZE_8 0x20
-#define READ_ENDIANNESS_ABCD 0
-#define READ_ENDIANNESS_DCBA 0x4
-#define READ_ENDIANNESS_BADC 0x8
-#define READ_ENDIANNESS_CDAB 0xC
-#define WRITE_ENDIANNESS_ABCD 0
-#define WRITE_ENDIANNESS_DCBA 0x1
-#define WRITE_ENDIANNESS_BADC 0x2
-#define WRITE_ENDIANNESS_CDAB 0x3
-
-/* various bits in configuration register EBI_CTRL_SIG_ACTLV */
-#define IORDY_ACTIVELEVEL_HIGH (1 << 14)
-#define ALE_ACTIVELEVEL_HIGH (1 << 8)
-
-/* bits in register EBI_SIG_LEVEL */
-#define IORDY_LEVEL_MASK 1
-
-static inline void ebi_wait(void)
-{
- while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE)
- ; /* wait */
-}
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include "vct.h"
-
-static u32 ebi_read(u32 addr)
-{
- addr &= ~0xFC000000;
-
- reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr);
- ebi_wait();
-
- return reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
-}
-
-static int ebi_write_u16(u32 addr, u32 data, int fetchIO)
-{
- u32 val = (data << 16);
-
- addr &= ~0xFC000000;
-
- ebi_wait();
-
- reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val);
- reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
- EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | addr);
- ebi_wait();
-
- if (fetchIO) {
- u32 counter = 0;
- while (!(reg_read(EBI_SIG_LEVEL(EBI_BASE)) & EXT_CPU_IORDY_SL)) {
- if (counter++ > 0xFFFFFF)
- return 1;
- }
- }
-
- return 0;
-}
-
-static u16 ebi_read_u16(u32 addr)
-{
- return ((ebi_read(addr) >> 16) & 0xFFFF);
-}
-
-static u8 ebi_read_u8(u32 addr)
-{
- u32 val = ebi_read(addr) >> 16;
-
- if (addr & 0x1)
- return val & 0xff;
- else
- return (val >> 8) & 0xff;
-}
-
-/*
- * EBI initialization for NOR FLASH access
- */
-int ebi_init_nor_flash(void)
-{
- reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000);
-
- reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002);
- reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50);
-
- reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113);
- reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000);
- reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113);
- reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011);
- reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000);
-
- return 0;
-}
-
-/*
- * Accessor functions replacing the "weak" functions in
- * drivers/mtd/cfi_flash.c
- */
-void flash_write8(u8 value, void *addr)
-{
- ebi_write_u16((u32)addr, value, 0);
-}
-
-void flash_write16(u16 value, void *addr)
-{
- ebi_write_u16((u32)addr, value, 0);
-}
-
-u8 flash_read8(void *addr)
-{
- return ebi_read_u8((u32)addr);
-}
-
-u16 flash_read16(void *addr)
-{
- return ebi_read_u16((u32)addr);
-}
-
-u32 flash_read32(void *addr)
-{
- return ((u32)ebi_read_u16((u32)addr) << 16) |
- ebi_read_u16((u32)addr + 2);
-}
-
-void *board_flash_read_memcpy(void *dest, const void *src, size_t count)
-{
- u16 *tmp = (u16 *)dest, *s = (u16 *)src;
- int i;
-
- for (i = 0; i < count; i += 2)
- *tmp++ = flash_read16(s++);
-
- return dest;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/onenand.h>
-#include "vct.h"
-
-#define BURST_SIZE_WORDS 4
-
-static u16 ebi_nand_read_word(void __iomem *addr)
-{
- reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr));
- ebi_wait();
-
- return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16;
-}
-
-static void ebi_nand_write_word(u16 data, void __iomem * addr)
-{
- ebi_wait();
- reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16));
- reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
- EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr);
- ebi_wait();
-}
-
-/*
- * EBI initialization for OneNAND FLASH access
- */
-int ebi_init_onenand(void)
-{
- reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000);
-
- reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002);
- reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50);
-
- reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002);
- reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */
-
- reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000);
- reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000);
- reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223);
- reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220);
- reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000);
- reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000);
- reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000);
- reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200);
-
- reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000);
- reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
-
- reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000);
- reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
-
- /* prepare DMA configuration for EBI */
- reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00);
-
- /* READ only no byte order change, TAG 1 used */
- reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004);
-
- reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */
- reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1);
- reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2);
- reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3);
-
- return 0;
-}
-
-static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len)
-{
- void *ret = dst;
- u16 *d = dst;
- u16 *s = (u16 *)src;
-
- len >>= 1;
- while (len-- > 0)
- *d++ = ebi_nand_read_word(s++);
-
- return ret;
-}
-
-static void *memcpy_32_from_onenand(void *dst, const void *src, unsigned int len)
-{
- void *ret = dst;
- u32 *d = (u32 *)dst;
- u32 s = (u32)src;
- u32 bytes_per_block = BURST_SIZE_WORDS * sizeof(int);
- u32 n_blocks = len / bytes_per_block;
- u32 block = 0;
- u32 burst_word;
-
- for (block = 0; block < n_blocks; block++) {
- /* Trigger read channel 3 */
- reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
- (EXT_DEVICE_CHANNEL_3 | (s + (block * bytes_per_block))));
- /* Poll status to see whether read has finished */
- ebi_wait();
-
- /* Squirrel the data away in a safe place */
- for (burst_word = 0; burst_word < BURST_SIZE_WORDS; burst_word++)
- *d++ = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
- }
-
- return ret;
-}
-
-static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len)
-{
- void *ret = dst;
- u16 *d = dst;
- u16 *s = (u16 *)src;
-
- len >>= 1;
- while (len-- > 0)
- ebi_nand_write_word(*s++, d++);
-
- return ret;
-}
-
-static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
-{
- struct onenand_chip *this = mtd->priv;
-
- if (ONENAND_CURRENT_BUFFERRAM(this)) {
- if (area == ONENAND_DATARAM)
- return mtd->writesize;
- if (area == ONENAND_SPARERAM)
- return mtd->oobsize;
- }
-
- return 0;
-}
-
-static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area,
- unsigned char *buffer, int offset,
- size_t count)
-{
- struct onenand_chip *this = mtd->priv;
- void __iomem *bufferram;
-
- bufferram = this->base + area;
- bufferram += onenand_bufferram_offset(mtd, area);
-
- if (count < 4)
- memcpy_16_from_onenand(buffer, bufferram + offset, count);
- else
- memcpy_32_from_onenand(buffer, bufferram + offset, count);
-
- return 0;
-}
-
-static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area,
- const unsigned char *buffer, int offset,
- size_t count)
-{
- struct onenand_chip *this = mtd->priv;
- void __iomem *bufferram;
-
- bufferram = this->base + area;
- bufferram += onenand_bufferram_offset(mtd, area);
-
- memcpy_16_to_onenand(bufferram + offset, buffer, count);
-
- return 0;
-}
-
-int onenand_board_init(struct mtd_info *mtd)
-{
- struct onenand_chip *chip = mtd->priv;
-
- /*
- * Insert board specific OneNAND access functions
- */
- chip->read_word = ebi_nand_read_word;
- chip->write_word = ebi_nand_write_word;
-
- chip->read_bufferram = ebi_read_bufferram;
- chip->write_bufferram = ebi_write_bufferram;
-
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include "vct.h"
-
-/*
- * EBI initialization for SMC911x access
- */
-int ebi_init_smc911x(void)
-{
- reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020);
- reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
-
- reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100);
- reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111);
-
- reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000);
- reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
-
- reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100);
- reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110);
-
- return 0;
-}
-
-/*
- * Accessor functions replacing the "weak" functions in
- * drivers/net/smc911x.c
- */
-u32 smc911x_reg_read(struct eth_device *dev, u32 addr)
-{
- volatile u32 data;
-
- addr += dev->iobase;
- reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
- ebi_wait();
- reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
- ebi_wait();
- data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
-
- return (data);
-}
-
-void smc911x_reg_write(struct eth_device *dev, u32 addr, u32 data)
-{
- addr += dev->iobase;
- reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
- ebi_wait();
- reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
- reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
- EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr);
- ebi_wait();
-}
-
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 data)
-{
- addr += dev->iobase;
- reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
- ebi_wait();
- reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
- reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
- EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr);
- ebi_wait();
-
- return;
-}
-
-u32 pkt_data_pull(struct eth_device *dev, u32 addr)
-{
- volatile u32 data;
-
- addr += dev->iobase;
- reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
- ebi_wait();
- reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
- ebi_wait();
- data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
-
- return data;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_DRIVER_SMC911X_BASE);
-#endif
- return rc;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Original Author Guenter Gebhardt
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#include <common.h>
-
-#include "vct.h"
-
-int vct_ehci_hcd_init(u32 *hccr, u32 *hcor)
-{
- int retval;
- u32 val;
- u32 addr;
-
- dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
- dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
- dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
- dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON);
- dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF);
-
- /* Wait until (DCGU_USBPHY_STAT == 7) */
- addr = DCGU_USBPHY_STAT(DCGU_BASE);
- val = reg_read(addr);
- while (val != 7)
- val = reg_read(addr);
-
- dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
- dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF);
-
- retval = scc_reset(SCC_USB_RW, 0);
- if (retval) {
- printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval);
- return retval;
- } else {
- retval = scc_reset(SCC_CPU1_SPDMA_RW, 0);
- if (retval) {
- printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n",
- retval);
- return retval;
- }
- }
-
- if (!retval) {
- /*
- * For the AGU bypass, where the SCC client provides full
- * physical address
- */
- scc_set_usb_address_generation_mode(1);
- scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
- USE_NO_FH, DMA_READ, 0);
- scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
- USE_NO_FH, DMA_WRITE, 0);
- scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
- USE_NO_FH, DMA_WRITE, 0);
- scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
- USE_NO_FH, DMA_READ, 0);
-
- /* Enable memory interface */
- scc_enable(SCC_USB_RW, 1);
-
- /* Start (start_cmd=0) DMAs */
- scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ);
- scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE);
- } else {
- printf("Cannot configure USB memory channel.\n");
- printf("USB can not access RAM. SCC configuration failed.\n");
- return retval;
- }
-
- /* Wait a short while */
- udelay(300000);
-
- reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
-
- /* Set EHCI structures and DATA in RAM */
- reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003);
- /* Set USBMODE to bigendian and set host mode */
- reg_write(USBH_USBMODE(USBH_BASE), 0x00000007);
-
- /*
- * USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for
- * 512 byte USB transfers on the bulk pipe to work properly.
- * Set USBH_BURSTSIZE to 0x00001c1c
- */
- reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
-
- /* Insert access register addresses */
- *hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE);
- *hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE);
-
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include "vct.h"
-
-/*
- * Find out to which of the 2 gpio modules the pin specified in the
- * argument belongs:
- * GPIO_MODULE yields 0 for pins 0 to 31,
- * 1 for pins 32 to 63
- */
-#define GPIO_MODULE(pin) ((pin) >> 5)
-
-/*
- * Bit position within a 32-bit peripheral register (where every
- * bit is one bitslice)
- */
-#define MASK(pin) (1 << ((pin) & 0x1F))
-#define BASE_ADDR(mod) module_base[mod]
-
-/*
- * Lookup table for transforming gpio module number 0 to 2 to
- * address offsets
- */
-static u32 module_base[] = {
- GPIO1_BASE,
- GPIO2_BASE
-};
-
-static void clrsetbits(u32 addr, u32 and_mask, u32 or_mask)
-{
- reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask);
-}
-
-int vct_gpio_dir(int pin, int dir)
-{
- u32 gpio_base;
-
- gpio_base = BASE_ADDR(GPIO_MODULE(pin));
-
- if (dir == 0)
- clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0);
- else
- clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin));
-
- return 0;
-}
-
-void vct_gpio_set(int pin, int val)
-{
- u32 gpio_base;
-
- gpio_base = BASE_ADDR(GPIO_MODULE(pin));
-
- if (val == 0)
- clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0);
- else
- clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin));
-}
-
-int vct_gpio_get(int pin)
-{
- u32 gpio_base;
- u32 value;
-
- gpio_base = BASE_ADDR(GPIO_MODULE(pin));
- value = reg_read(GPIO_EXT_PORTA(gpio_base));
-
- return ((value & MASK(pin)) ? 1 : 0);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#include <common.h>
-#include <linux/errno.h>
-
-#include "vct.h"
-
-/*
- * List of statically defined buffers per SCC.
- * The first entry in the table is the number of fixed buffers
- * followed by the list of buffer IDs
- */
-static u32 buffer_list_0[] = { 6, 120, 121, 122, 123, 139, 140 };
-static u32 buffer_list_1[] = { 6, 120, 121, 122, 123, 139, 140 };
-static u32 buffer_list_2[] = { 5, 124, 125, 126, 139, 140 };
-static u32 buffer_list_3[] = { 5, 124, 125, 126, 139, 140 };
-static u32 buffer_list_4[] = { 5, 124, 125, 126, 139, 140 };
-static u32 buffer_list_5[] = { 3, 127, 139, 140 };
-static u32 buffer_list_6[] = { 3, 127, 139, 140 };
-static u32 buffer_list_7[] = { 6, 128, 129, 130, 131, 139, 140 };
-static u32 buffer_list_8[] = { 6, 128, 129, 130, 131, 139, 140 };
-static u32 buffer_list_9[] = { 5, 124, 125, 126, 139, 140 };
-static u32 buffer_list_10[] = { 5, 124, 125, 126, 139, 140 };
-static u32 buffer_list_11[] = { 5, 124, 125, 126, 139, 140 };
-static u32 buffer_list_12[] = { 6, 132, 133, 134, 135, 139, 140 };
-static u32 buffer_list_13[] = { 6, 132, 133, 134, 135, 139, 140 };
-static u32 buffer_list_14[] = { 4, 137, 138, 139, 140 };
-static u32 buffer_list_15[] = { 6, 136, 136, 137, 138, 139, 140 };
-
-/** Issue#7674 (new) - DP/DVP buffer assignment */
-static u32 buffer_list_16[] = { 6, 106, 108, 109, 107, 139, 140 };
-static u32 buffer_list_17[] = { 6, 106, 110, 107, 111, 139, 140 };
-static u32 buffer_list_18[] = { 6, 106, 113, 107, 114, 139, 140 };
-static u32 buffer_list_19[] = { 3, 112, 139, 140 };
-static u32 buffer_list_20[] = { 35, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 79, 80, 81, 82, 83, 84, 85, 86, 139, 140 };
-static u32 buffer_list_21[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 139, 140 };
-static u32 buffer_list_22[] = { 81, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
- 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
- 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60,
- 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72,
- 73, 74, 75, 76, 77, 78, 139, 140 };
-static u32 buffer_list_23[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 88, 89, 139, 140 };
-static u32 buffer_list_24[] = { 6, 90, 91, 92, 93, 139, 140 };
-static u32 buffer_list_25[] = { 18, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,
- 100, 101, 102, 103, 104, 105, 139, 140 };
-static u32 buffer_list_26[] = { 5, 94, 95, 96, 139, 140 };
-static u32 buffer_list_27[] = { 5, 97, 98, 99, 139, 140 };
-static u32 buffer_list_28[] = { 5, 100, 101, 102, 139, 140 };
-static u32 buffer_list_29[] = { 5, 103, 104, 105, 139, 140 };
-static u32 buffer_list_30[] = { 10, 108, 109, 110, 111, 113, 114, 116, 117,
- 139, 140 };
-static u32 buffer_list_31[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114,
- 115, 116, 117, 139, 140 };
-static u32 buffer_list_32[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114,
- 115, 116, 117, 139, 140 };
-static u32 buffer_list_33[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 139, 140 };
-static u32 buffer_list_34[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 139, 140 };
-static u32 buffer_list_35[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 87, 139, 140 };
-static u32 buffer_list_36[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 87, 139, 140 };
-static u32 buffer_list_37[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 139, 140 };
-static u32 buffer_list_38[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 118, 119, 139, 140 };
-static u32 buffer_list_39[] = { 91, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
- 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
- 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60,
- 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72,
- 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84,
- 85, 86, 118, 119, 139, 140 };
-static u32 buffer_list_40[] = { 0 };
-
-/*
- * List of statically defined vcid.csize values.
- * The first entry in the table is the number of possible csize values
- * followed by the list of data path values in bits.
- */
-static u32 csize_list_0[] = { 2, 0, 1 };
-static u32 csize_list_1[] = { 2, 0, 1 };
-static u32 csize_list_2[] = { 1, 1 };
-static u32 csize_list_3[] = { 1, 1 };
-static u32 csize_list_4[] = { 1, 1 };
-static u32 csize_list_5[] = { 1, 0 };
-static u32 csize_list_6[] = { 1, 0 };
-static u32 csize_list_7[] = { 1, 1 };
-static u32 csize_list_8[] = { 1, 1 };
-static u32 csize_list_9[] = { 1, 1 };
-static u32 csize_list_10[] = { 1, 1 };
-static u32 csize_list_11[] = { 1, 1 };
-static u32 csize_list_12[] = { 1, 1 };
-static u32 csize_list_13[] = { 1, 1 };
-static u32 csize_list_14[] = { 1, 2 };
-static u32 csize_list_15[] = { 1, 4 };
-static u32 csize_list_16[] = { 3, 0, 1, 2 };
-static u32 csize_list_17[] = { 3, 0, 1, 2 };
-static u32 csize_list_18[] = { 3, 0, 1, 2 };
-static u32 csize_list_19[] = { 1, 2 };
-static u32 csize_list_20[] = { 1, 0 };
-static u32 csize_list_21[] = { 1, 0 };
-static u32 csize_list_22[] = { 1, 2 };
-static u32 csize_list_23[] = { 1, 3 };
-static u32 csize_list_24[] = { 1, 3 };
-static u32 csize_list_25[] = { 1, 3 };
-static u32 csize_list_26[] = { 1, 0 };
-static u32 csize_list_27[] = { 1, 0 };
-static u32 csize_list_28[] = { 1, 0 };
-static u32 csize_list_29[] = { 1, 0 };
-static u32 csize_list_30[] = { 1, 2 };
-static u32 csize_list_31[] = { 1, 2 };
-static u32 csize_list_32[] = { 1, 2 };
-static u32 csize_list_33[] = { 1, 2 };
-static u32 csize_list_34[] = { 1, 2 };
-static u32 csize_list_35[] = { 1, 2 };
-static u32 csize_list_36[] = { 1, 2 };
-static u32 csize_list_37[] = { 2, 0, 1 };
-static u32 csize_list_38[] = { 1, 2 };
-static u32 csize_list_39[] = { 1, 3 };
-static u32 csize_list_40[] = { 1, 3 };
-
-/*
- * SCC_Configuration table
- */
-static const struct scc_descriptor scc_descriptor_table[] = {
-/* scn scc_name profile SCC scc_id mci_id rd wr m p fh si cfg sta */
- {"fe_", "fe_3dcomb_wr", STRM_P, SCC0_BASE, 0, 0, 0, 4, 1, 1, 0, 0, 0, 1,
- buffer_list_0, csize_list_0},
- {"fe_", "fe_3dcomb_rd", STRM_P, SCC1_BASE, 1, 18, 4, 0, 1, 1, 0, 1, 0,
- 1, buffer_list_1, csize_list_1},
- {"di_", "di_tnr_wr", STRM_P, SCC2_BASE, 2, 1, 0, 3, 1, 1, 0, 2, 0, 1,
- buffer_list_2, csize_list_2},
- {"di_", "di_tnr_field_rd", STRM_P, SCC3_BASE, 3, 19, 3, 0, 1, 1, 0, 3,
- 0, 1, buffer_list_3, csize_list_3},
- {"di_", "di_tnr_frame_rd", STRM_P, SCC4_BASE, 4, 20, 3, 0, 1, 1, 0, 4,
- 0, 1, buffer_list_4, csize_list_4},
- {"di_", "di_mval_wr", STRM_P, SCC5_BASE, 5, 2, 0, 1, 1, 1, 0, 5, 0, 1,
- buffer_list_5, csize_list_5},
- {"di_", "di_mval_rd", STRM_P, SCC6_BASE, 6, 21, 1, 0, 1, 1, 0, 6, 0, 1,
- buffer_list_6, csize_list_6},
- {"rc_", "rc_frame_wr", STRM_P, SCC7_BASE, 7, 3, 0, 4, 1, 1, 0, 7, 0, 1,
- buffer_list_7, csize_list_7},
- {"rc_", "rc_frame0_rd", STRM_P, SCC8_BASE, 8, 22, 4, 0, 1, 1, 0, 8, 0,
- 1, buffer_list_8, csize_list_8},
- {"opt", "opt_field0_rd", STRM_P, SCC9_BASE, 9, 23, 3, 0, 1, 1, 0, 9, 0,
- 1, buffer_list_9, csize_list_9},
- {"opt", "opt_field1_rd", STRM_P, SCC10_BASE, 10, 24, 3, 0, 1, 1, 0, 10,
- 0, 1, buffer_list_10, csize_list_10},
- {"opt", "opt_field2_rd", STRM_P, SCC11_BASE, 11, 25, 3, 0, 1, 1, 0, 11,
- 0, 1, buffer_list_11, csize_list_11},
- {"pip", "pip_frame_wr", STRM_P, SCC12_BASE, 12, 4, 0, 4, 1, 1, 0, 12, 0,
- 1, buffer_list_12, csize_list_12},
- {"pip", "pip_frame_rd", STRM_P, SCC13_BASE, 13, 26, 4, 0, 1, 1, 0, 13,
- 0, 1, buffer_list_13, csize_list_13},
- {"dp_", "dp_agpu_rd", STRM_P, SCC14_BASE, 14, 27, 2, 0, 2, 1, 0, 14, 0,
- 1, buffer_list_14, csize_list_14},
- {"ewa", "ewarp_rw", SRMD, SCC15_BASE, 15, 11, 1, 1, 0, 0, 0, -1, 0, 0,
- buffer_list_15, csize_list_15},
- {"dp_", "dp_osd_rd", STRM_P, SCC16_BASE, 16, 28, 3, 0, 2, 1, 0, 15, 0,
- 1, buffer_list_16, csize_list_16},
- {"dp_", "dp_graphic_rd", STRM_P, SCC17_BASE, 17, 29, 3, 0, 2, 1, 0, 16,
- 0, 1, buffer_list_17, csize_list_17},
- {"dvp", "dvp_osd_rd", STRM_P, SCC18_BASE, 18, 30, 2, 0, 2, 1, 0, 17, 0,
- 1, buffer_list_18, csize_list_18},
- {"dvp", "dvp_vbi_rd", STRM_D, SCC19_BASE, 19, 31, 1, 0, 0, 1, 0, -1, 0,
- 0, buffer_list_19, csize_list_19},
- {"tsi", "tsio_wr", STRM_P, SCC20_BASE, 20, 5, 0, 8, 2, 1, 1, -1, 0, 0,
- buffer_list_20, csize_list_20},
- {"tsi", "tsio_rd", STRM_P, SCC21_BASE, 21, 32, 4, 0, 2, 1, 1, -1, 0, 0,
- buffer_list_21, csize_list_21},
- {"tsd", "tsd_wr", SRMD, SCC22_BASE, 22, 6, 0, 64, 0, 0, 1, -1, 0, 0,
- buffer_list_22, csize_list_22},
- {"vd_", "vd_ud_st_rw", SRMD, SCC23_BASE, 23, 12, 2, 2, 0, 0, 1, -1, 0,
- 0, buffer_list_23, csize_list_23},
- {"vd_", "vd_frr_rd", SRMD, SCC24_BASE, 24, 33, 4, 0, 0, 0, 0, -1, 0, 0,
- buffer_list_24, csize_list_24},
- {"vd_", "vd_frw_disp_wr", SRMD, SCC25_BASE, 25, 7, 0, 16, 0, 0, 0, -1,
- 0, 0, buffer_list_25, csize_list_25},
- {"mr_", "mr_vd_m_y_rd", STRM_P, SCC26_BASE, 26, 34, 3, 0, 2, 1, 0, 18,
- 0, 1, buffer_list_26, csize_list_26},
- {"mr_", "mr_vd_m_c_rd", STRM_P, SCC27_BASE, 27, 35, 3, 0, 2, 1, 0, 19,
- 0, 1, buffer_list_27, csize_list_27},
- {"mr_", "mr_vd_s_y_rd", STRM_P, SCC28_BASE, 28, 36, 3, 0, 2, 1, 0, 20,
- 0, 1, buffer_list_28, csize_list_28},
- {"mr_", "mr_vd_s_c_rd", STRM_P, SCC29_BASE, 29, 37, 3, 0, 2, 1, 0, 21,
- 0, 1, buffer_list_29, csize_list_29},
- {"ga_", "ga_wr", STRM_P, SCC30_BASE, 30, 8, 0, 1, 1, 1, 0, -1, 1, 1,
- buffer_list_30, csize_list_30},
- {"ga_", "ga_src1_rd", STRM_P, SCC31_BASE, 31, 38, 1, 0, 1, 1, 0, -1, 1,
- 1, buffer_list_31, csize_list_31},
- {"ga_", "ga_src2_rd", STRM_P, SCC32_BASE, 32, 39, 1, 0, 1, 1, 0, -1, 1,
- 1, buffer_list_32, csize_list_32},
- {"ad_", "ad_rd", STRM_D, SCC33_BASE, 33, 40, 2, 0, 0, 1, 1, -1, 0, 0,
- buffer_list_33, csize_list_33},
- {"ad_", "ad_wr", STRM_D, SCC34_BASE, 34, 9, 0, 3, 0, 1, 1, -1, 0, 0,
- buffer_list_34, csize_list_34},
- {"abp", "abp_rd", STRM_D, SCC35_BASE, 35, 41, 5, 0, 0, 1, 1, -1, 0, 0,
- buffer_list_35, csize_list_35},
- {"abp", "abp_wr", STRM_D, SCC36_BASE, 36, 10, 0, 3, 0, 1, 1, -1, 0, 0,
- buffer_list_36, csize_list_36},
- {"ebi", "ebi_rw", STRM_P, SCC37_BASE, 37, 13, 4, 4, 2, 1, 1, -1, 0, 0,
- buffer_list_37, csize_list_37},
- {"usb", "usb_rw", SRMD, SCC38_BASE, 38, 14, 1, 1, 0, 0, 1, -1, 0, 0,
- buffer_list_38, csize_list_38},
- {"cpu", "cpu1_spdma_rw", SRMD, SCC39_BASE, 39, 15, 1, 1, 0, 0, 1, -1, 0,
- 0, buffer_list_39, csize_list_39},
- {"cpu", "cpu1_bridge_rw", SRMD, SCC40_BASE, 40, 16, 0, 0, 0, 0, 0, -1,
- 0, 0, buffer_list_40, csize_list_40},
-};
-
-/* DMA state structures for read and write channels for each SCC */
-
-static struct scc_dma_state scc_state_rd_0[] = { {-1} };
-static struct scc_dma_state scc_state_wr_0[] = { {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_rd_1[] = { {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_1[] = { {-1} };
-static struct scc_dma_state scc_state_rd_2[] = { {-1} };
-static struct scc_dma_state scc_state_wr_2[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_rd_3[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_3[] = { {-1} };
-static struct scc_dma_state scc_state_rd_4[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_4[] = { {-1} };
-static struct scc_dma_state scc_state_rd_5[] = { {-1} };
-static struct scc_dma_state scc_state_wr_5[] = { {0} };
-static struct scc_dma_state scc_state_rd_6[] = { {0} };
-static struct scc_dma_state scc_state_wr_6[] = { {-1} };
-static struct scc_dma_state scc_state_rd_7[] = { {-1} };
-static struct scc_dma_state scc_state_wr_7[] = { {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_rd_8[] = { {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_8[] = { {-1} };
-static struct scc_dma_state scc_state_rd_9[] = { {0}, {0}, {0}, };
-static struct scc_dma_state scc_state_wr_9[] = { {-1} };
-static struct scc_dma_state scc_state_rd_10[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_10[] = { {-1} };
-static struct scc_dma_state scc_state_rd_11[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_11[] = { {-1} };
-static struct scc_dma_state scc_state_rd_12[] = { {-1} };
-static struct scc_dma_state scc_state_wr_12[] = { {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_rd_13[] = { {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_13[] = { {-1} };
-static struct scc_dma_state scc_state_rd_14[] = { {0}, {0} };
-static struct scc_dma_state scc_state_wr_14[] = { {-1} };
-static struct scc_dma_state scc_state_rd_15[] = { {0} };
-static struct scc_dma_state scc_state_wr_15[] = { {0} };
-static struct scc_dma_state scc_state_rd_16[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_16[] = { {-1} };
-static struct scc_dma_state scc_state_rd_17[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_17[] = { {-1} };
-static struct scc_dma_state scc_state_rd_18[] = { {0}, {0} };
-static struct scc_dma_state scc_state_wr_18[] = { {-1} };
-static struct scc_dma_state scc_state_rd_19[] = { {0} };
-static struct scc_dma_state scc_state_wr_19[] = { {-1} };
-static struct scc_dma_state scc_state_rd_20[] = { {-1} };
-static struct scc_dma_state scc_state_wr_20[] = {
- {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_rd_21[] = { {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_21[] = { {-1} };
-static struct scc_dma_state scc_state_rd_22[] = { {-1} };
-static struct scc_dma_state scc_state_wr_22[] = {
- {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
- {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
- {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
- {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
- {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_rd_23[] = { {0}, {0} };
-static struct scc_dma_state scc_state_wr_23[] = { {0}, {0} };
-static struct scc_dma_state scc_state_rd_24[] = { {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_24[] = { {-1} };
-static struct scc_dma_state scc_state_rd_25[] = { {-1} };
-static struct scc_dma_state scc_state_wr_25[] = {
- {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
- {0}, {0} };
-static struct scc_dma_state scc_state_rd_26[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_26[] = { {-1} };
-static struct scc_dma_state scc_state_rd_27[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_27[] = { {-1} };
-static struct scc_dma_state scc_state_rd_28[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_28[] = { {-1} };
-static struct scc_dma_state scc_state_rd_29[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_29[] = { {-1} };
-static struct scc_dma_state scc_state_rd_30[] = { {-1} };
-static struct scc_dma_state scc_state_wr_30[] = { {0} };
-static struct scc_dma_state scc_state_rd_31[] = { {0} };
-static struct scc_dma_state scc_state_wr_31[] = { {-1} };
-static struct scc_dma_state scc_state_rd_32[] = { {0} };
-static struct scc_dma_state scc_state_wr_32[] = { {-1} };
-static struct scc_dma_state scc_state_rd_33[] = { {0}, {0} };
-static struct scc_dma_state scc_state_wr_33[] = { {-1} };
-static struct scc_dma_state scc_state_rd_34[] = { {-1} };
-static struct scc_dma_state scc_state_wr_34[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_rd_35[] = { {0}, {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_35[] = { {-1} };
-static struct scc_dma_state scc_state_rd_36[] = { {-1} };
-static struct scc_dma_state scc_state_wr_36[] = { {0}, {0}, {0} };
-static struct scc_dma_state scc_state_rd_37[] = { {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_wr_37[] = { {0}, {0}, {0}, {0} };
-static struct scc_dma_state scc_state_rd_38[] = { {0} };
-static struct scc_dma_state scc_state_wr_38[] = { {0} };
-static struct scc_dma_state scc_state_rd_39[] = { {0} };
-static struct scc_dma_state scc_state_wr_39[] = { {0} };
-static struct scc_dma_state scc_state_rd_40[] = { {-1} };
-static struct scc_dma_state scc_state_wr_40[] = { {-1} };
-
-/* DMA state references to access from the driver */
-static struct scc_dma_state *scc_state_rd[] = {
- scc_state_rd_0,
- scc_state_rd_1,
- scc_state_rd_2,
- scc_state_rd_3,
- scc_state_rd_4,
- scc_state_rd_5,
- scc_state_rd_6,
- scc_state_rd_7,
- scc_state_rd_8,
- scc_state_rd_9,
- scc_state_rd_10,
- scc_state_rd_11,
- scc_state_rd_12,
- scc_state_rd_13,
- scc_state_rd_14,
- scc_state_rd_15,
- scc_state_rd_16,
- scc_state_rd_17,
- scc_state_rd_18,
- scc_state_rd_19,
- scc_state_rd_20,
- scc_state_rd_21,
- scc_state_rd_22,
- scc_state_rd_23,
- scc_state_rd_24,
- scc_state_rd_25,
- scc_state_rd_26,
- scc_state_rd_27,
- scc_state_rd_28,
- scc_state_rd_29,
- scc_state_rd_30,
- scc_state_rd_31,
- scc_state_rd_32,
- scc_state_rd_33,
- scc_state_rd_34,
- scc_state_rd_35,
- scc_state_rd_36,
- scc_state_rd_37,
- scc_state_rd_38,
- scc_state_rd_39,
- scc_state_rd_40,
-};
-
-static struct scc_dma_state *scc_state_wr[] = {
- scc_state_wr_0,
- scc_state_wr_1,
- scc_state_wr_2,
- scc_state_wr_3,
- scc_state_wr_4,
- scc_state_wr_5,
- scc_state_wr_6,
- scc_state_wr_7,
- scc_state_wr_8,
- scc_state_wr_9,
- scc_state_wr_10,
- scc_state_wr_11,
- scc_state_wr_12,
- scc_state_wr_13,
- scc_state_wr_14,
- scc_state_wr_15,
- scc_state_wr_16,
- scc_state_wr_17,
- scc_state_wr_18,
- scc_state_wr_19,
- scc_state_wr_20,
- scc_state_wr_21,
- scc_state_wr_22,
- scc_state_wr_23,
- scc_state_wr_24,
- scc_state_wr_25,
- scc_state_wr_26,
- scc_state_wr_27,
- scc_state_wr_28,
- scc_state_wr_29,
- scc_state_wr_30,
- scc_state_wr_31,
- scc_state_wr_32,
- scc_state_wr_33,
- scc_state_wr_34,
- scc_state_wr_35,
- scc_state_wr_36,
- scc_state_wr_37,
- scc_state_wr_38,
- scc_state_wr_39,
- scc_state_wr_40,
-};
-
-static u32 scc_takeover_mode = SCC_TO_IMMEDIATE;
-
-/* Change mode of the SPDMA for given direction */
-static u32 scc_agu_mode_sp = AGU_BYPASS;
-
-/* Change mode of the USB for given direction */
-static u32 scc_agu_mode_usb = AGU_BYPASS;
-
-static union scc_softwareconfiguration scc_software_configuration[SCC_MAX];
-
-static u32 dma_fsm[4][4] = {
- /* DMA_CMD_RESET DMA_CMD_SETUP DMA_CMD_START DMA_CMD_STOP */
- /* DMA_STATE_RESET */
- {DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_ERROR, DMA_STATE_ERROR},
- /* DMA_STATE_SETUP */
- {DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_START, DMA_STATE_SETUP},
- /* DMA_STATE_START */
- {DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_START, DMA_STATE_SETUP},
- /* DMA_STATE_ERROR */
- {DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_ERROR, DMA_STATE_ERROR},
-};
-
-static void dma_state_process(struct scc_dma_state *dma_state, u32 cmd)
-{
- dma_state->dma_status = dma_fsm[dma_state->dma_status][cmd];
- dma_state->dma_cmd = cmd;
-}
-
-static void dma_state_process_dma_command(struct scc_dma_state *dma_state,
- u32 dma_cmd)
-{
- dma_state->dma_cmd = dma_cmd;
- switch (dma_cmd) {
- case DMA_START:
- case DMA_START_FH_RESET:
- dma_state_process(dma_state, DMA_CMD_START);
- break;
- case DMA_STOP:
- dma_state_process(dma_state, DMA_CMD_STOP);
- break;
- default:
- break;
- }
-}
-
-static void scc_takeover_dma(enum scc_id id, u32 dma_id, u32 drs)
-{
- union scc_cmd dma_cmd;
-
- dma_cmd.reg = 0;
-
- /* Prepare the takeover for the DMA channel */
- dma_cmd.bits.action = DMA_TAKEOVER;
- dma_cmd.bits.id = dma_id;
- dma_cmd.bits.rid = TO_DMA_CFG; /* this is DMA_CFG register takeover */
- if (drs == DMA_WRITE)
- dma_cmd.bits.drs = DMA_WRITE;
-
- reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg);
-}
-
-int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs)
-{
- union scc_cmd dma_cmd;
- struct scc_dma_state *dma_state;
-
- if ((id >= SCC_MAX) || (id < 0))
- return -EINVAL;
-
- dma_cmd.reg = 0;
-
- /* Prepare the takeover for the DMA channel */
- dma_cmd.bits.action = cmd;
- dma_cmd.bits.id = dma_id;
- if (drs == DMA_WRITE) {
- dma_cmd.bits.drs = DMA_WRITE;
- dma_state = &scc_state_wr[id][dma_id];
- } else {
- dma_state = &scc_state_rd[id][dma_id];
- }
-
- dma_state->scc_id = id;
- dma_state->dma_id = dma_id;
- dma_state_process_dma_command(dma_state, cmd);
-
- reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg);
-
- return 0;
-}
-
-int scc_set_usb_address_generation_mode(u32 agu_mode)
-{
- if (AGU_ACTIVE == agu_mode) {
- /* Ensure both DMAs are stopped */
- scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_WRITE);
- scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_READ);
- } else {
- agu_mode = AGU_BYPASS;
- }
-
- scc_agu_mode_usb = agu_mode;
-
- return 0;
-}
-
-int scc_setup_dma(enum scc_id id, u32 buffer_tag,
- u32 type, u32 fh_mode, u32 drs, u32 dma_id)
-{
- struct scc_dma_state *dma_state;
- int return_value = 0;
- union scc_dma_cfg dma_cfg;
- u32 *buffer_tag_list;
- u32 tag_count, t, t_valid;
-
- if ((id >= SCC_MAX) || (id < 0))
- return -EINVAL;
-
- buffer_tag_list = scc_descriptor_table[id].buffer_tag_list;
-
- /* if the register is only configured by hw, cannot write! */
- if (1 == scc_descriptor_table[id].hw_dma_cfg)
- return -EACCES;
-
- if (DMA_WRITE == drs) {
- if (dma_id >= scc_descriptor_table[id].p_dma_channels_wr)
- return -EINVAL;
- dma_state = &scc_state_wr[id][dma_id];
- } else {
- if (dma_id >= scc_descriptor_table[id].p_dma_channels_rd)
- return -EINVAL;
- dma_state = &scc_state_rd[id][dma_id];
- }
-
- /* Compose the DMA configuration register */
- tag_count = buffer_tag_list[0];
- t_valid = 0;
- for (t = 1; t <= tag_count; t++) {
- if (buffer_tag == buffer_tag_list[t]) {
- /* Tag found - validate */
- t_valid = 1;
- break;
- }
- }
-
- if (!t_valid)
- return -EACCES;
-
- /*
- * Read the register first -- two functions write into the register
- * it does not make sense to read the DMA config back, because there
- * are two register configuration sets (drs)
- */
- dma_cfg.reg = 0;
- dma_cfg.bits.buffer_id = buffer_tag;
- dma_state_process(dma_state, DMA_CMD_SETUP);
-
- /*
- * This is Packet CFG set select - usable for TSIO, EBI and those SCCs
- * which habe 2 packet configs
- */
- dma_cfg.bits.packet_cfg_id =
- scc_software_configuration[id].bits.packet_select;
-
- if (type == DMA_CYCLIC)
- dma_cfg.bits.buffer_type = 1;
- else
- dma_cfg.bits.buffer_type = 0;
-
- if (fh_mode == USE_FH)
- dma_cfg.bits.fh_mode = 1;
- else
- dma_cfg.bits.fh_mode = 0;
-
- if (id == SCC_CPU1_SPDMA_RW)
- dma_cfg.bits.agu_mode = scc_agu_mode_sp;
-
- if (id == SCC_USB_RW)
- dma_cfg.bits.agu_mode = scc_agu_mode_usb;
-
- reg_write(SCC_DMA_CFG(scc_descriptor_table[id].base_address),
- dma_cfg.reg);
-
- /* The DMA_CFG needs a takeover! */
- if (SCC_TO_IMMEDIATE == scc_takeover_mode)
- scc_takeover_dma(id, dma_id, drs);
-
- /* if (buffer_tag is not used) */
- dma_state->buffer_tag = buffer_tag;
-
- dma_state->scc_id = id;
- dma_state->dma_id = dma_id;
-
- return return_value;
-}
-
-int scc_enable(enum scc_id id, u32 value)
-{
- if ((id >= SCC_MAX) || (id < 0))
- return -EINVAL;
-
- if (value == 0) {
- scc_software_configuration[id].bits.enable_status = 0;
- } else {
- value = 1;
- scc_software_configuration[id].bits.enable_status = 1;
- }
- reg_write(SCC_ENABLE(scc_descriptor_table[id].base_address), value);
-
- return 0;
-}
-
-static inline void ehb(void)
-{
- __asm__ __volatile__(
- " .set mips32r2 \n"
- " ehb \n"
- " .set mips0 \n");
-}
-
-int scc_reset(enum scc_id id, u32 value)
-{
- if ((id >= SCC_MAX) || (id < 0))
- return -EINVAL;
-
- /* Invert value to the strait logic from the negative hardware logic */
- if (value == 0)
- value = 1;
- else
- value = 0;
-
- /* Write the value to the register */
- reg_write(SCC_RESET(scc_descriptor_table[id].base_address), value);
-
- /* sync flush */
- asm("sync"); /* request bus write queue flush */
- ehb(); /* wait until previous bus commit instr has finished */
- asm("nop"); /* wait for flush to occur */
- asm("nop"); /* wait for flush to occur */
-
- udelay(100);
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#ifndef _SCC_H
-#define _SCC_H
-
-#define DMA_READ 0 /* SCC read DMA */
-#define DMA_WRITE 1 /* SCC write DMA */
-
-#define DMA_LINEAR 0 /* DMA linear buffer access method */
-#define DMA_CYCLIC 1 /* DMA cyclic buffer access method */
-
-#define DMA_START 0 /* DMA command - start DMA */
-#define DMA_STOP 1 /* DMA command - stop DMA */
-#define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */
-#define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */
-
-#define AGU_ACTIVE 0 /* enable AGU address calculation */
-#define AGU_BYPASS 1 /* set AGU to bypass mode */
-
-#define USE_NO_FH 0 /* order the DMA to not use FH */
-#define USE_FH 1 /* order the DMA to work with FH*/
-
-#define SCC_DBG_IDLE 0 /* DEBUG status (idle interfaces) */
-#define SCC_DBG_SYNC_RES 0x0001 /* synchronuous reset */
-
-#define SCC_TO_IMMEDIATE 1 /* takeover command issued immediately*/
-#define TO_DMA_CFG 2 /* takeover command for the DMA config*/
-
-#define DMA_CMD_RESET 0
-#define DMA_CMD_SETUP 1
-#define DMA_CMD_START 2
-#define DMA_CMD_STOP 3
-
-#define DMA_STATE_RESET 0
-#define DMA_STATE_SETUP 1
-#define DMA_STATE_START 2
-#define DMA_STATE_ERROR 3
-
-#define SRMD 0
-#define STRM_D 1
-#define STRM_P 2
-
-/*
- * Slowest Monterey domain is DVP 27 MHz (324/27 = 12; 12*16 = 192 CPU clocks)
- */
-#define RESET_TIME 2 /* cycle calc see in SCC_Reset */
-
-struct scc_descriptor {
- char *pu_name; /* PU identifier */
- char *scc_instance; /* SCC Name */
- u32 profile; /* SCC VCI_D profile */
-
- u32 base_address; /* base address of the SCC unit reg shell*/
-
- /* SCS Interconnect configuration */
- u32 p_scc_id; /* instance number of SCC unit */
- u32 p_mci_id; /* memory channel ID */
-
- /* DMA Registers configuration */
- u32 p_dma_channels_rd; /* Number of Read DMA channels */
- u32 p_dma_channels_wr; /* Number of Write DMA channels */
-
- u32 p_dma_packet_desc; /* Number of packet descriptors */
- u32 p_dma_mci_desc; /* Number of MCI_CFG Descriptors */
-
- int use_fh; /* the flag tells if SCC uses an FH */
-
- int p_si2ocp_id; /* instance number of SI2OCP unit */
- int hw_dma_cfg; /* HW or SW DMA config flag */
- int hw_dma_start; /* HW or SW DMA start/stop flag */
-
- u32 *buffer_tag_list; /* list of the buffer tags available */
- u32 *csize_list; /* list of the valid CSIZE values */
-};
-
-struct scc_dma_state {
- u32 scc_id:8; /* SCC id */
- u32 dma_id:8; /* DMA id, used for match with array idx*/
- u32 buffer_tag:8; /* mem buf tag, assigned to this DMA */
- u32 dma_status:2; /* state of DMA, of the DMA_STATE_ const*/
- u32 dma_drs:2; /* DMA dir, either DMA_READ or DMA_WRITE*/
- u32 dma_cmd:4; /* last executed command on this DMA */
-};
-
-union scc_cmd {
- u32 reg;
- struct {
- u32 res1:19; /* reserved */
- u32 drs:1; /* DMA Register Set */
- u32 rid:2; /* Register Identifier */
- u32 id:6; /* DMA Identifier */
- u32 action:4; /* DMA Command encoding */
- } bits;
-};
-
-union scc_dma_cfg {
- u32 reg;
- struct {
- u32 res1:17; /* reserved */
- u32 agu_mode:1; /* AGU Mode */
- u32 res2:1; /* reserved */
- u32 fh_mode:1; /* Fifo Handler */
- u32 buffer_type:1; /* Defines type of mem buffers */
- u32 mci_cfg_id:1; /* MCI_CFG register selector */
- u32 packet_cfg_id:1; /* PACKET_CFG register selector */
- u32 buffer_id:8; /* DMA Buffer Identifier */
- } bits;
-};
-
-union scc_debug {
- u32 reg;
- struct {
- u32 res1:20; /* reserved */
- u32 arg:8; /* SCC Debug Command Argument (#) */
- u32 cmd:4; /* SCC Debug Command Register */
- } bits;
-};
-
-union scc_softwareconfiguration {
- u32 reg;
- struct {
- u32 res1:28; /* reserved */
- u32 clock_status:1; /* clock on/off */
- u32 packet_select:1; /* active SCC packet id */
- u32 enable_status:1; /* enabled [1/0] */
- u32 active_status:1; /* 1=active 0=reset */
- } bits;
-};
-
-/*
- * System on Chip Channel ID
- */
-enum scc_id {
- SCC_NULL = -1, /* illegal SCC identifier */
- SCC_FE_3DCOMB_WR, /* SCC_FE_3DCOMB Write channel */
- SCC_FE_3DCOMB_RD, /* SCC_FE_3DCOMB Read channel */
- SCC_DI_TNR_WR, /* SCC_DI_TNR Write channel */
- SCC_DI_TNR_FIELD_RD, /* SCC_DI_TNR_FIELD Read channel */
- SCC_DI_TNR_FRAME_RD, /* SCC_DI_TNR_FRAME Read channel */
- SCC_DI_MVAL_WR, /* SCC_DI_MVAL Write channel */
- SCC_DI_MVAL_RD, /* SCC_DI_MVAL Read channel */
- SCC_RC_FRAME_WR, /* SCC_RC_FRAME Write channel */
- SCC_RC_FRAME0_RD, /* SCC_RC_FRAME0 Read channel */
- SCC_OPT_FIELD0_RD, /* SCC_OPT_FIELD0 Read channel */
- SCC_OPT_FIELD1_RD, /* SCC_OPT_FIELD1 Read channel */
- SCC_OPT_FIELD2_RD, /* SCC_OPT_FIELD2 Read channel */
- SCC_PIP_FRAME_WR, /* SCC_PIP_FRAME Write channel */
- SCC_PIP_FRAME_RD, /* SCC_PIP_FRAME Read channel */
- SCC_DP_AGPU_RD, /* SCC_DP_AGPU Read channel */
- SCC_EWARP_RW, /* SCC_EWARP Read/Write channel */
- SCC_DP_OSD_RD, /* SCC_DP_OSD Read channel */
- SCC_DP_GRAPHIC_RD, /* SCC_DP_GRAPHIC Read channel */
- SCC_DVP_OSD_RD, /* SCC_DVP_OSD Read channel */
- SCC_DVP_VBI_RD, /* SCC_DVP_VBI Read channel */
- SCC_TSIO_WR, /* SCC_TSIO Write channel */
- SCC_TSIO_RD, /* SCC_TSIO Read channel */
- SCC_TSD_WR, /* SCC_TSD Write channel */
- SCC_VD_UD_ST_RW, /* SCC_VD_UD_ST Read/Write channel */
- SCC_VD_FRR_RD, /* SCC_VD_FRR Read channel */
- SCC_VD_FRW_DISP_WR, /* SCC_VD_FRW_DISP Write channel */
- SCC_MR_VD_M_Y_RD, /* SCC_MR_VD_M_Y Read channel */
- SCC_MR_VD_M_C_RD, /* SCC_MR_VD_M_C Read channel */
- SCC_MR_VD_S_Y_RD, /* SCC_MR_VD_S_Y Read channel */
- SCC_MR_VD_S_C_RD, /* SCC_MR_VD_S_C Read channel */
- SCC_GA_WR, /* SCC_GA Write channel */
- SCC_GA_SRC1_RD, /* SCC_GA_SRC1 Read channel */
- SCC_GA_SRC2_RD, /* SCC_GA_SRC2 Read channel */
- SCC_AD_RD, /* SCC_AD Read channel */
- SCC_AD_WR, /* SCC_AD Write channel */
- SCC_ABP_RD, /* SCC_ABP Read channel */
- SCC_ABP_WR, /* SCC_ABP Write channel */
- SCC_EBI_RW, /* SCC_EBI Read/Write channel */
- SCC_USB_RW, /* SCC_USB Read/Write channel */
- SCC_CPU1_SPDMA_RW, /* SCC_CPU1_SPDMA Read/Write channel */
- SCC_CPU1_BRIDGE_RW, /* SCC_CPU1_BRIDGE Read/Write channel */
- SCC_MAX /* maximum limit on the SCC id */
-};
-
-int scc_set_usb_address_generation_mode(u32 agu_mode);
-int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs);
-int scc_setup_dma(enum scc_id id, u32 buffer_tag,
- u32 type, u32 fh_mode, u32 drs, u32 dma_id);
-int scc_enable(enum scc_id id, u32 value);
-int scc_reset(enum scc_id id, u32 value);
-
-#endif /* _SCC_H */
+++ /dev/null
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright 2005, Seagate Technology LLC
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#undef DEBUG
-
-#include <common.h>
-#include <command.h>
-#include <config.h>
-#include <net.h>
-
-#include "vct.h"
-
-#define SMSC9118_BASE CONFIG_DRIVER_SMC911X_BASE
-#define BYTE_TEST (SMSC9118_BASE + 0x64)
-#define GPIO_CFG (SMSC9118_BASE + 0x88)
-#define MAC_CSR_CMD (SMSC9118_BASE + 0xA4)
-#define MAC_CSR_CMD_CSR_BUSY (0x80000000)
-#define MAC_CSR_CMD_RNW (0x40000000)
-#define MAC_RD_CMD(reg) ((reg & 0x000000FF) | \
- (MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_RNW))
-#define MAC_WR_CMD(reg) ((reg & 0x000000FF) | \
- (MAC_CSR_CMD_CSR_BUSY))
-#define MAC_CSR_DATA (SMSC9118_BASE + 0xA8)
-#define E2P_CMD (SMSC9118_BASE + 0xB0)
-#define E2P_CMD_EPC_BUSY_ (0x80000000UL) /* Self Clearing */
-#define E2P_CMD_EPC_CMD_ (0x70000000UL) /* R/W */
-#define E2P_CMD_EPC_CMD_READ_ (0x00000000UL) /* R/W */
-#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000UL) /* R/W */
-#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000UL) /* R/W */
-#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000UL) /* R/W */
-#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000UL) /* R/W */
-#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000UL) /* R/W */
-#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000UL) /* R/W */
-#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL) /* R/W */
-#define E2P_CMD_EPC_TIMEOUT_ (0x00000200UL) /* R */
-#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100UL) /* RO */
-#define E2P_CMD_EPC_ADDR_ (0x000000FFUL) /* R/W */
-#define E2P_DATA (SMSC9118_BASE + 0xB4)
-
-#define MAC_ADDRH (0x2)
-#define MAC_ADDRL (0x3)
-
-#define MAC_TIMEOUT 200
-
-#define HIBYTE(word) ((u8)(((u16)(word)) >> 8))
-#define LOBYTE(word) ((u8)(((u16)(word)) & 0x00FFU))
-#define HIWORD(dword) ((u16)(((u32)(dword)) >> 16))
-#define LOWORD(dword) ((u16)(((u32)(dword)) & 0x0000FFFFUL))
-
-static int mac_busy(int req_to)
-{
- int timeout = req_to;
-
- while (timeout--) {
- if (!(smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY))
- goto done;
- }
- return 1; /* Timeout */
-
-done:
- return 0; /* No timeout */
-}
-
-static ulong get_mac_reg(int reg)
-{
- ulong reg_val = 0xffffffff;
-
- if (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) {
- printf("get_mac_reg: previous command not complete\n");
- goto done;
- }
-
- smc911x_reg_write(MAC_CSR_CMD, MAC_RD_CMD(reg));
- udelay(10000);
-
- if (mac_busy(MAC_TIMEOUT) == 1) {
- printf("get_mac_reg: timeout waiting for response from MAC\n");
- goto done;
- }
-
- reg_val = smc911x_reg_read(MAC_CSR_DATA);
-
-done:
- return (reg_val);
-}
-
-static ulong eeprom_enable_access(void)
-{
- ulong gpio;
-
- gpio = smc911x_reg_read(GPIO_CFG);
- debug("%s: gpio= 0x%08lx ---> 0x%08lx\n", __func__, gpio,
- (gpio & 0xFF0FFFFFUL));
-
- smc911x_reg_write(GPIO_CFG, (gpio & 0xFF0FFFFFUL));
- return gpio;
-}
-
-static void eeprom_disable_access(ulong gpio)
-{
- debug("%s: gpio= 0x%08lx\n", __func__, gpio);
- smc911x_reg_write(GPIO_CFG, gpio);
-}
-
-static int eeprom_is_mac_address_loaded(void)
-{
- int ret;
-
- ret = smc911x_reg_read(MAC_CSR_CMD) & E2P_CMD_MAC_ADDR_LOADED_;
- debug("%s: ret = %x\n", __func__, ret);
-
- return ret;
-}
-
-static int eeprom_read_location(unchar address, u8 *data)
-{
- ulong timeout = 100000;
- ulong temp = 0;
-
- if ((temp = smc911x_reg_read(E2P_CMD)) & E2P_CMD_EPC_BUSY_) {
- printf("%s: Busy at start, E2P_CMD=0x%08lX\n", __func__, temp);
- return 0;
- }
-
- smc911x_reg_write(E2P_CMD,
- (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_ |
- ((ulong) address)));
-
- while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
- udelay(10);
- timeout--;
- }
-
- if (timeout == 0) {
- printf("Timeout\n");
- return 0;
- }
- (*data) = (unchar) (smc911x_reg_read(E2P_DATA));
- debug("%s: ret = %x\n", __func__, (*data));
-
- return 1;
-}
-
-static int eeprom_enable_erase_and_write(void)
-{
- ulong timeout = 100000;
-
- if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
- printf("%s: Busy at start\n", __func__);
- return 0;
- }
- smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_));
-
- while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
- udelay(10);
- timeout--;
- }
-
- if (timeout == 0) {
- printf("Timeout[1]\n");
- return 0;
- }
-
- return 1;
-}
-
-static int eeprom_disable_erase_and_write(void)
-{
- ulong timeout = 100000;
-
- if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
- printf("%s: Busy at start\n", __func__);
- return 0;
- }
- smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWDS_));
-
- while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
- udelay(10);
- timeout--;
- }
-
- if (timeout == 0) {
- printf("Timeout[2]\n");
- return 0;
- }
-
- return 1;
-}
-
-static int eeprom_write_location(unchar address, unchar data)
-{
- ulong timeout = 100000;
-
- debug("%s: address: %x data = %x\n", __func__, address, data);
-
- if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
- printf("%s: Busy at start\n", __func__);
- return 0;
- }
-
- smc911x_reg_write(E2P_DATA, ((ulong) data));
- smc911x_reg_write(E2P_CMD,
- (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_ |
- ((ulong) address)));
-
- while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
- udelay(10);
- timeout--;
- }
-
- if (timeout == 0) {
- printf("Timeout[3]\n");
- return 0;
- }
-
- return 1;
-}
-
-static int eeprom_erase_all(void)
-{
- ulong timeout = 100000;
-
- if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
- printf("%s: Busy at start\n", __func__);
- return 0;
- }
-
- smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_ERAL_));
-
- while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
- udelay(10);
- timeout--;
- }
-
- if (timeout == 0) {
- printf("Timeout[4]\n");
- return 0;
- }
-
- return 1;
-}
-
-static int eeprom_reload(void)
-{
- ulong timeout = 100000;
-
- if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
- printf("%s: Busy at start\n", __func__);
- return -1;
- }
- smc911x_reg_write(E2P_CMD,
- (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
-
- while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
- udelay(10);
- timeout--;
- }
-
- if (timeout == 0)
- return 0;
-
- return 1;
-}
-
-static int eeprom_save_mac_address(ulong dwHi16, ulong dwLo32)
-{
- int result = 0;
-
- debug("%s: dwHI: 0x%08lx dwLO: %08lx, \n", __func__, dwHi16, dwLo32);
-
- if (!eeprom_enable_erase_and_write())
- goto DONE;
- if (!eeprom_erase_all())
- goto DONE;
- if (!eeprom_write_location(0, 0xA5))
- goto DONE;
- if (!eeprom_write_location(1, LOBYTE(LOWORD(dwLo32))))
- goto DONE;
- if (!eeprom_write_location(2, HIBYTE(LOWORD(dwLo32))))
- goto DONE;
- if (!eeprom_write_location(3, LOBYTE(HIWORD(dwLo32))))
- goto DONE;
- if (!eeprom_write_location(4, HIBYTE(HIWORD(dwLo32))))
- goto DONE;
- if (!eeprom_write_location(5, LOBYTE(LOWORD(dwHi16))))
- goto DONE;
- if (!eeprom_write_location(6, HIBYTE(LOWORD(dwHi16))))
- goto DONE;
- if (!eeprom_disable_erase_and_write())
- goto DONE;
-
- result = 1;
-
-DONE:
- return result;
-}
-
-static int do_eeprom_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unchar data = 0, index = 0;
- ulong gpio_old_val;
-
- gpio_old_val = eeprom_enable_access();
-
- printf("EEPROM content: \n");
- for (index = 0; index < 8; index++) {
- if (eeprom_read_location(index, &data))
- printf("%02x ", data);
- else
- printf("FAILED");
- }
-
- eeprom_disable_access(gpio_old_val);
- printf("\n");
-
- return 0;
-}
-
-static int do_eeprom_erase_all(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- eeprom_erase_all();
-
- return 0;
-}
-
-static int do_eeprom_save_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong hi16, lo32;
- unchar ethaddr[6], i;
- ulong gpio;
- char *tmp, *end;
-
- tmp = argv[1];
- for (i = 0; i < 6; i++) {
- ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
- if (tmp)
- tmp = (*end) ? end + 1 : end;
- }
-
- hi16 = (ethaddr[5] << 8) | (ethaddr[4]);
- lo32 = (ethaddr[3] << 24) | (ethaddr[2] << 16) |
- (ethaddr[1] << 8) | (ethaddr[0]);
-
- gpio = eeprom_enable_access();
-
- eeprom_save_mac_address(hi16, lo32);
-
- eeprom_reload();
-
- /* Check new values */
- if (eeprom_is_mac_address_loaded()) {
- ulong mac_hi16, mac_lo32;
-
- mac_hi16 = get_mac_reg(MAC_ADDRH);
- mac_lo32 = get_mac_reg(MAC_ADDRL);
- printf("New MAC address: %lx, %lx\n", mac_hi16, mac_lo32);
- } else {
- printf("Address is not reloaded \n");
- }
- eeprom_disable_access(gpio);
-
- return 0;
-}
-
-U_BOOT_CMD(smcee, 1, 0, do_eeprom_erase_all,
- "smcee - Erase content of SMC EEPROM",);
-
-U_BOOT_CMD(smced, 1, 0, do_eeprom_dump,
- "smced - Dump content of SMC EEPROM",);
-
-U_BOOT_CMD(smcew, 2, 0, do_eeprom_save_mac,
- "smcew - Write MAC address to SMC EEPROM\n",
- "aa:bb:cc:dd:ee:ff new mac address");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#include <common.h>
-#include "vct.h"
-
-typedef union _TOP_PINMUX_t
-{
- u32 reg;
- struct {
- u32 res : 24; /* reserved */
- u32 drive : 2; /* Driver strength */
- u32 slew : 1; /* Slew rate */
- u32 strig : 1; /* Schmitt trigger input*/
- u32 pu_pd : 2; /* Pull up/ pull down */
- u32 funsel : 2; /* Pin function */
- } Bits;
-} TOP_PINMUX_t;
-
-#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
-
-static TOP_PINMUX_t top_read_pin(int pin)
-{
- TOP_PINMUX_t reg;
-
- switch (pin) {
- case 2:
- case 3:
- case 6:
- case 9:
- reg.reg = 0xdeadbeef;
- break;
- case 4:
- reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE));
- break;
- case 5:
- reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE));
- break;
- case 7:
- reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE));
- break;
- case 8:
- reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE));
- break;
- case 10:
- case 11:
- case 12:
- case 13:
- case 14:
- case 15:
- case 16:
- reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
- ((pin - 10) * 4));
- break;
- default:
- reg.reg = reg_read(TOP_BASE + (pin * 4));
- break;
- }
-
- return reg;
-}
-
-static void top_write_pin(int pin, TOP_PINMUX_t reg)
-{
-
- switch (pin) {
- case 4:
- reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg);
- break;
- case 5:
- reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg);
- break;
- case 7:
- reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg);
- break;
- case 8:
- reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg);
- break;
- case 10:
- case 11:
- case 12:
- case 13:
- case 14:
- case 15:
- case 16:
- reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
- ((pin - 10) * 4), reg.reg);
- break;
- default:
- reg_write(TOP_BASE + (pin * 4), reg.reg);
- break;
- }
-}
-
-int top_set_pin(int pin, int func)
-{
- TOP_PINMUX_t reg;
-
- /* check global range */
- if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3))
- return -1; /* pin number or function out of valid range */
-
- /* check undefined values; */
- if ((pin == 2) || (pin == 3) || (pin == 6) || (pin == 9))
- return -1; /* pin number out of valid range */
-
- reg = top_read_pin(pin);
- reg.Bits.funsel = func;
- top_write_pin(pin, reg);
-
- return 0;
-}
-
-#endif
-
-#if defined(CONFIG_VCT_PLATINUMAVC)
-
-int top_set_pin(int pin, int func)
-{
- TOP_PINMUX_t reg;
-
- /* check global range */
- if ((pin < 0) || (pin > 158))
- return -1; /* pin number or function out of valid range */
-
- reg.reg = reg_read(TOP_BASE + (pin * 4));
- reg.Bits.funsel = func;
- reg_write(TOP_BASE + (pin * 4), reg.reg);
-
- return 0;
-}
-
-#endif
-
-void vct_pin_mux_initialize(void)
-{
-#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
- top_set_pin(34, 01); /* EBI_CS0 */
- top_set_pin(33, 01); /* EBI_CS1 */
- top_set_pin(32, 01); /* EBI_CS2 */
- top_set_pin(100, 02); /* EBI_CS3 */
- top_set_pin(101, 02); /* EBI_CS4 */
- top_set_pin(102, 02); /* EBI_CS5 */
- top_set_pin(103, 02); /* EBI_CS6 */
- top_set_pin(104, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */
- top_set_pin(35, 01); /* EBI_ALE */
- top_set_pin(36, 01); /* EBI_ADDR15 */
- top_set_pin(37, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */
- top_set_pin(38, 01); /* EBI_ADDR13 */
- top_set_pin(39, 01); /* EBI_ADDR12 */
- top_set_pin(40, 01); /* EBI_ADDR11 */
- top_set_pin(41, 01); /* EBI_ADDR10 */
- top_set_pin(42, 01); /* EBI_ADDR9 */
- top_set_pin(43, 01); /* EBI_ADDR8 */
- top_set_pin(44, 01); /* EBI_ADDR7 */
- top_set_pin(45, 01); /* EBI_ADDR6 */
- top_set_pin(46, 01); /* EBI_ADDR5 */
- top_set_pin(47, 01); /* EBI_ADDR4 */
- top_set_pin(48, 01); /* EBI_ADDR3 */
- top_set_pin(49, 01); /* EBI_ADDR2 */
- top_set_pin(50, 01); /* EBI_ADDR1 */
- top_set_pin(51, 01); /* EBI_ADDR0 */
- top_set_pin(52, 01); /* EBI_DIR */
- top_set_pin(53, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */
- top_set_pin(54, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */
- top_set_pin(55, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */
- top_set_pin(56, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */
- top_set_pin(57, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */
- top_set_pin(58, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */
- top_set_pin(59, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */
- top_set_pin(60, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */
- top_set_pin(61, 01); /* EBI_DAT7 */
- top_set_pin(62, 01); /* EBI_DAT6 */
- top_set_pin(63, 01); /* EBI_DAT5 */
- top_set_pin(64, 01); /* EBI_DAT4 */
- top_set_pin(65, 01); /* EBI_DAT3 */
- top_set_pin(66, 01); /* EBI_DAT2 */
- top_set_pin(67, 01); /* EBI_DAT1 */
- top_set_pin(68, 01); /* EBI_DAT0 */
- top_set_pin(69, 01); /* EBI_IORD */
- top_set_pin(70, 01); /* EBI_IOWR */
- top_set_pin(71, 01); /* EBI_WE */
- top_set_pin(72, 01); /* EBI_OE */
- top_set_pin(73, 01); /* EBI_IORDY */
- top_set_pin(95, 02); /* EBI_EBI_DMACK*/
- top_set_pin(112, 02); /* EBI_IRQ0 */
- top_set_pin(111, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */
- top_set_pin(107, 02); /* EBI_IRQ2 */
- top_set_pin(108, 02); /* EBI_IRQ3 */
- top_set_pin(30, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */
- top_set_pin(31, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */
- top_set_pin(105, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */
- top_set_pin(106, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */
- top_set_pin(109, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */
- top_set_pin(110, 02); /* EBI_BURST_CLK */
-#endif
-
-#if defined(CONFIG_VCT_PLATINUMAVC)
- top_set_pin(19, 01); /* EBI_CS0 */
- top_set_pin(18, 01); /* EBI_CS1 */
- top_set_pin(17, 01); /* EBI_CS2 */
- top_set_pin(92, 02); /* EBI_CS3 */
- top_set_pin(93, 02); /* EBI_CS4 */
- top_set_pin(95, 02); /* EBI_CS6 */
- top_set_pin(96, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */
- top_set_pin(20, 01); /* EBI_ALE */
- top_set_pin(21, 01); /* EBI_ADDR15 */
- top_set_pin(22, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */
- top_set_pin(23, 01); /* EBI_ADDR13 */
- top_set_pin(24, 01); /* EBI_ADDR12 */
- top_set_pin(25, 01); /* EBI_ADDR11 */
- top_set_pin(26, 01); /* EBI_ADDR10 */
- top_set_pin(27, 01); /* EBI_ADDR9 */
- top_set_pin(28, 01); /* EBI_ADDR8 */
- top_set_pin(29, 01); /* EBI_ADDR7 */
- top_set_pin(30, 01); /* EBI_ADDR6 */
- top_set_pin(31, 01); /* EBI_ADDR5 */
- top_set_pin(32, 01); /* EBI_ADDR4 */
- top_set_pin(33, 01); /* EBI_ADDR3 */
- top_set_pin(34, 01); /* EBI_ADDR2 */
- top_set_pin(35, 01); /* EBI_ADDR1 */
- top_set_pin(36, 01); /* EBI_ADDR0 */
- top_set_pin(37, 01); /* EBI_DIR */
- top_set_pin(38, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */
- top_set_pin(39, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */
- top_set_pin(40, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */
- top_set_pin(41, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */
- top_set_pin(42, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */
- top_set_pin(43, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */
- top_set_pin(44, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */
- top_set_pin(45, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */
- top_set_pin(46, 01); /* EBI_DAT7 */
- top_set_pin(47, 01); /* EBI_DAT6 */
- top_set_pin(48, 01); /* EBI_DAT5 */
- top_set_pin(49, 01); /* EBI_DAT4 */
- top_set_pin(50, 01); /* EBI_DAT3 */
- top_set_pin(51, 01); /* EBI_DAT2 */
- top_set_pin(52, 01); /* EBI_DAT1 */
- top_set_pin(53, 01); /* EBI_DAT0 */
- top_set_pin(54, 01); /* EBI_IORD */
- top_set_pin(55, 01); /* EBI_IOWR */
- top_set_pin(56, 01); /* EBI_WE */
- top_set_pin(57, 01); /* EBI_OE */
- top_set_pin(58, 01); /* EBI_IORDY */
- top_set_pin(87, 02); /* EBI_EBI_DMACK*/
- top_set_pin(106, 02); /* EBI_IRQ0 */
- top_set_pin(105, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */
- top_set_pin(101, 02); /* EBI_IRQ2 */
- top_set_pin(102, 02); /* EBI_IRQ3 */
- top_set_pin(15, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */
- top_set_pin(16, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */
- top_set_pin(99, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */
- top_set_pin(100, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */
- top_set_pin(103, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */
- top_set_pin(104, 02); /* EBI_BURST_CLK */
-#endif
-
- /* I2C: Configure I2C-2 as GPIO to enable soft-i2c */
- top_set_pin(0, 2); /* SCL2 on GPIO 11 */
- top_set_pin(1, 2); /* SDA2 on GPIO 10 */
-
- /* UART pins */
-#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
- top_set_pin(141, 1);
- top_set_pin(143, 1);
-#endif
-#if defined(CONFIG_VCT_PLATINUMAVC)
- top_set_pin(107, 1);
- top_set_pin(109, 1);
-#endif
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <netdev.h>
-#include <asm/mipsregs.h>
-#include "vct.h"
-
-#if defined(CONFIG_VCT_PREMIUM)
-#define BOARD_NAME "PremiumD"
-#elif defined(CONFIG_VCT_PLATINUM)
-#define BOARD_NAME "PlatinumD"
-#elif defined(CONFIG_VCT_PLATINUMAVC)
-#define BOARD_NAME "PlatinumAVC"
-#else
-#error "vct: No board variant defined!"
-#endif
-
-#if defined(CONFIG_VCT_ONENAND)
-#define BOARD_NAME_ADD " OneNAND"
-#else
-#define BOARD_NAME_ADD " NOR"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * First initialize the PIN mulitplexing
- */
- vct_pin_mux_initialize();
-
- /*
- * Init the EBI very early so that FLASH can be accessed
- */
- ebi_initialize();
-
- return 0;
-}
-
-void _machine_restart(void)
-{
- reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT);
- reg_write(WDT_TORR(WDT_BASE), 0x00);
- reg_write(WDT_CR(WDT_BASE), 0x1D);
-
- /*
- * Now wait for the watchdog to trigger the reset
- */
- udelay(1000000);
-}
-
-/*
- * SDRAM is already configured by the bootstrap code, only return the
- * auto-detected size here
- */
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_MBYTES_SDRAM << 20);
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = env_get_f("serial#", buf, sizeof(buf));
- u32 config0 = read_c0_prid();
-
- if ((config0 & 0xff0000) == PRID_COMP_LEGACY
- && (config0 & 0xff00) == PRID_IMP_LX4280) {
- puts("Board: MDED \n");
- printf("CPU: LX4280 id: 0x%02x, rev: 0x%02x\n",
- (config0 >> 8) & 0xFF, config0 & 0xFF);
- } else if ((config0 & 0xff0000) == PRID_COMP_MIPS
- && (config0 & 0xff00) == PRID_IMP_VGC) {
- u32 jedec_id = *((u32 *) 0xBEBC71A0);
- if ((((jedec_id) >> 12) & 0xFF) == 0x40) {
- puts("Board: VGCA \n");
- } else if ((((jedec_id) >> 12) & 0xFF) == 0x48
- || (((jedec_id) >> 12) & 0xFF) == 0x49) {
- puts("Board: VGCB \n");
- }
- printf("CPU: MIPS 4K id: 0x%02x, rev: 0x%02x\n",
- (config0 >> 8) & 0xFF, config0 & 0xFF);
- } else if (config0 == 0x19378) {
- printf("CPU: MIPS 24K id: 0x%02x, rev: 0x%02x\n",
- (config0 >> 8) & 0xFF, config0 & 0xFF);
- } else {
- printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24,
- config0);
- }
-
- printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD);
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#include <asm/io.h>
-
-#include "bcu.h"
-#include "dcgu.h"
-#include "ebi.h"
-#include "scc.h"
-
-#ifdef CONFIG_VCT_PREMIUM
-/* Global start address of all memory mapped registers */
-#define REG_GLOBAL_START_ADDR 0xbf800000
-#define TOP_BASE 0x000c8000
-
-#include "vcth/reg_ebi.h"
-#include "vcth/reg_dcgu.h"
-#include "vcth/reg_wdt.h"
-#include "vcth/reg_gpio.h"
-#include "vcth/reg_fwsram.h"
-#include "vcth/reg_scc.h"
-#include "vcth/reg_usbh.h"
-#endif
-
-#ifdef CONFIG_VCT_PLATINUM
-/* Global start address of all memory mapped registers */
-#define REG_GLOBAL_START_ADDR 0xbf800000
-#define TOP_BASE 0x000c8000
-
-#include "vcth2/reg_ebi.h"
-#include "vcth/reg_dcgu.h"
-#include "vcth/reg_wdt.h"
-#include "vcth/reg_gpio.h"
-#include "vcth/reg_fwsram.h"
-#include "vcth/reg_scc.h"
-#include "vcth/reg_usbh.h"
-#endif
-
-#ifdef CONFIG_VCT_PLATINUMAVC
-/* Global start address of all memory mapped registers */
-#define REG_GLOBAL_START_ADDR 0xbdc00000
-#define TOP_BASE 0x00050000
-
-#include "vctv/reg_ebi.h"
-#include "vctv/reg_dcgu.h"
-#include "vctv/reg_wdt.h"
-#include "vctv/reg_gpio.h"
-#endif
-
-#ifndef _VCT_H
-#define _VCT_H
-
-/*
- * Defines
- */
-#define PRID_COMP_LEGACY 0x000000
-#define PRID_COMP_MIPS 0x010000
-#define PRID_IMP_LX4280 0xc200
-#define PRID_IMP_VGC 0x9000
-
-/*
- * Prototypes
- */
-int ebi_initialize(void);
-int ebi_init_nor_flash(void);
-int ebi_init_onenand(void);
-int ebi_init_smc911x(void);
-u32 smc911x_reg_read(u32 addr);
-void smc911x_reg_write(u32 addr, u32 data);
-int top_set_pin(int pin, int func);
-void vct_pin_mux_initialize(void);
-
-/*
- * static inlines
- */
-static inline void reg_write(u32 addr, u32 data)
-{
- void *reg = (void *)(addr + REG_GLOBAL_START_ADDR);
- __raw_writel(data, reg);
-}
-
-static inline u32 reg_read(u32 addr)
-{
- const void *reg = (const void *)(addr + REG_GLOBAL_START_ADDR);
- return __raw_readl(reg);
-}
-
-#endif /* _VCT_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008-2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#define DCGU_BASE 0x00084000
-
-/* Relative offsets of the register adresses */
-
-#define DCGU_CLK_EN1_OFFS 0x00000010
-#define DCGU_CLK_EN1(base) ((base) + DCGU_CLK_EN1_OFFS)
-#define DCGU_CLK_EN2_OFFS 0x00000014
-#define DCGU_CLK_EN2(base) ((base) + DCGU_CLK_EN2_OFFS)
-#define DCGU_RESET_UNIT1_OFFS 0x00000018
-#define DCGU_RESET_UNIT1(base) ((base) + DCGU_RESET_UNIT1_OFFS)
-#define DCGU_USBPHY_STAT_OFFS 0x00000054
-#define DCGU_USBPHY_STAT(base) ((base) + DCGU_USBPHY_STAT_OFFS)
-#define DCGU_EN_WDT_RESET_OFFS 0x00000064
-#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS)
-
-/* The magic value to write in order to activate the WDT */
-#define DCGU_MAGIC_WDT 0x1909
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#ifndef _REG_EBI_PREMIUM_H_
-#define _REG_EBI_PREMIUM_H_
-
-#define EBI_BASE 0x00000000
-
-/* Relative offsets of the register adresses */
-
-#define EBI_CPU_IO_ACCS_OFFS 0x00000000
-#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
-#define EBI_IO_ACCS_DATA_OFFS 0x00000004
-#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
-#define EBI_CTRL_OFFS 0x00000008
-#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
-#define EBI_IRQ_MASK_OFFS 0x00000010
-#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
-#define EBI_TAG1_SYS_ID_OFFS 0x00000030
-#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
-#define EBI_TAG2_SYS_ID_OFFS 0x00000040
-#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
-#define EBI_TAG3_SYS_ID_OFFS 0x00000050
-#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
-#define EBI_TAG4_SYS_ID_OFFS 0x00000060
-#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
-#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
-#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
-#define EBI_STATUS_OFFS 0x00000080
-#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
-#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
-#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
-#define EBI_SIG_LEVEL_OFFS 0x00000088
-#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
-#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
-#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
-#define EBI_EXT_ADDR_OFFS 0x000000A0
-#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
-#define EBI_IRQ_STATUS_OFFS 0x000000B0
-#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
-#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
-#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
-#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
-#define EBI_DEV1_CONFIG1_OFFS 0x00000108
-#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
-#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
-#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
-#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
-#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
-#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
-#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
-#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
-#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
-#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
-#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
-#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
-#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
-#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
-#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
-#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
-#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
-#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
-#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
-#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
-#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
-#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
-#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
-#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
-#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
-#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
-#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
-#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
-#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
-#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
-#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
-#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
-#define EBI_DEV2_CONFIG1_OFFS 0x00000208
-#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
-#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
-#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
-#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
-#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
-#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
-#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
-#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
-#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
-#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
-#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
-#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
-#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
-#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
-#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
-#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
-#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
-#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
-#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
-#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
-#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
-#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
-#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
-#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
-#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
-#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
-#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
-#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
-#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
-#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
-#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
-#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
-#define EBI_DEV3_CONFIG1_OFFS 0x00000308
-#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
-#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
-#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
-#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
-#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
-#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
-#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
-#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
-#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
-#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
-#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
-#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
-#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
-#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
-#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
-#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
-#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
-#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
-#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
-#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
-#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
-#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
-#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
-#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
-#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
-#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
-#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
-#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
-#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
-#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
-#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
-#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
-#define EBI_DEV4_CONFIG1_OFFS 0x00000408
-#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
-#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
-#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
-#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
-#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
-#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
-#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
-#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
-#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
-#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
-#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
-#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
-#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
-#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
-#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
-#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
-#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
-#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
-#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
-#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
-#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
-#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
-#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
-#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
-#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
-#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
-#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
-#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
-#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
-#define EBI_CNT_FL_PROGR_OFFS 0x00000904
-#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
-#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
-#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
-#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
-#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
-#define EBI_CNT_ACK_OFFS 0x00000918
-#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
-#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
-#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
-#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
-#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
-#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
-#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
-#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
-#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
-#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
-#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
-#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
-#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
-#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
-#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
-#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
-#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
-#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
-#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
-#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
-#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
-#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
-#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
-#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
-#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
-#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
-#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
-#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
-#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
-#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
-#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-/*
- * Premium & Platinum register addresses/definitions seem to be
- * identical, so we only need to use one file for both platforms.
- */
-
-#ifndef _REG_FWSRAM_H_
-#define _REG_FWSRAM_H_
-
-#define FWSRAM_BASE 0x00030000
-
-/* Relative offsets of the register adresses */
-
-#define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000
-#define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS)
-#define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004
-#define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS)
-#define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008
-#define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS)
-#define FWSRAM_TOP_CID1_H_OFFS 0x0000200C
-#define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS)
-#define FWSRAM_TOP_CID1_L_OFFS 0x00002010
-#define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS)
-#define FWSRAM_TOP_CID2_H_OFFS 0x00002014
-#define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS)
-#define FWSRAM_TOP_CID2_L_OFFS 0x00002018
-#define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS)
-#define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C
-#define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS)
-#define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040
-#define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS)
-#define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044
-#define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS)
-#define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048
-#define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS)
-#define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C
-#define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS)
-#define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050
-#define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS)
-#define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054
-#define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS)
-#define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058
-#define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS)
-#define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C
-#define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS)
-#define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060
-#define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS)
-#define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064
-#define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS)
-#define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068
-#define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#define GPIO1_BASE 0x00088000
-#define GPIO2_BASE 0x0008c000
-
-/* Instances */
-#define GPIO_INSTANCES 2
-
-/* Relative offsets of the register adresses */
-#define GPIO_SWPORTA_DR_OFFS 0x00000000
-#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS)
-#define GPIO_SWPORTA_DDR_OFFS 0x00000004
-#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS)
-#define GPIO_EXT_PORTA_OFFS 0x00000050
-#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#ifndef _REG_SCC_PREMIUM_H_
-#define _REG_SCC_PREMIUM_H_
-
-#define SCC0_BASE 0x00110000
-#define SCC1_BASE 0x00110080
-#define SCC2_BASE 0x00110100
-#define SCC3_BASE 0x00110180
-#define SCC4_BASE 0x00110200
-#define SCC5_BASE 0x00110280
-#define SCC6_BASE 0x00110300
-#define SCC7_BASE 0x00110380
-#define SCC8_BASE 0x00110400
-#define SCC9_BASE 0x00110480
-#define SCC10_BASE 0x00110500
-#define SCC11_BASE 0x00110580
-#define SCC12_BASE 0x00110600
-#define SCC13_BASE 0x00110680
-#define SCC14_BASE 0x00110700
-#define SCC15_BASE 0x00110780
-#define SCC16_BASE 0x00110800
-#define SCC17_BASE 0x00110880
-#define SCC18_BASE 0x00110900
-#define SCC19_BASE 0x00110980
-#define SCC20_BASE 0x00110a00
-#define SCC21_BASE 0x00110a80
-#define SCC22_BASE 0x00110b00
-#define SCC23_BASE 0x00110b80
-#define SCC24_BASE 0x00110c00
-#define SCC25_BASE 0x00110c80
-#define SCC26_BASE 0x00110d00
-#define SCC27_BASE 0x00110d80
-#define SCC28_BASE 0x00110e00
-#define SCC29_BASE 0x00110e80
-#define SCC30_BASE 0x00110f00
-#define SCC31_BASE 0x00110f80
-#define SCC32_BASE 0x00111000
-#define SCC33_BASE 0x00111080
-#define SCC34_BASE 0x00111100
-#define SCC35_BASE 0x00111180
-#define SCC36_BASE 0x00111200
-#define SCC37_BASE 0x00111280
-#define SCC38_BASE 0x00111300
-#define SCC39_BASE 0x00111380
-#define SCC40_BASE 0x00111400
-
-/* Relative offsets of the register adresses */
-
-#define SCC_ENABLE_OFFS 0x00000000
-#define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS)
-#define SCC_RESET_OFFS 0x00000004
-#define SCC_RESET(base) ((base) + SCC_RESET_OFFS)
-#define SCC_VCID_OFFS 0x00000008
-#define SCC_VCID(base) ((base) + SCC_VCID_OFFS)
-#define SCC_MCI_CFG_OFFS 0x0000000C
-#define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS)
-#define SCC_PACKET_CFG1_OFFS 0x00000010
-#define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS)
-#define SCC_PACKET_CFG2_OFFS 0x00000014
-#define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS)
-#define SCC_PACKET_CFG3_OFFS 0x00000018
-#define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS)
-#define SCC_DMA_CFG_OFFS 0x0000001C
-#define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS)
-#define SCC_CMD_OFFS 0x00000020
-#define SCC_CMD(base) ((base) + SCC_CMD_OFFS)
-#define SCC_PRIO_OFFS 0x00000024
-#define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS)
-#define SCC_DEBUG_OFFS 0x00000028
-#define SCC_DEBUG(base) ((base) + SCC_DEBUG_OFFS)
-#define SCC_STATUS_OFFS 0x0000002C
-#define SCC_STATUS(base) ((base) + SCC_STATUS_OFFS)
-#define SCC_IMR_OFFS 0x00000030
-#define SCC_IMR(base) ((base) + SCC_IMR_OFFS)
-#define SCC_ISR_OFFS 0x00000034
-#define SCC_ISR(base) ((base) + SCC_ISR_OFFS)
-#define SCC_DMA_OFFSET_OFFS 0x00000038
-#define SCC_DMA_OFFSET(base) ((base) + SCC_DMA_OFFSET_OFFS)
-#define SCC_RS_CTLSTS_OFFS 0x0000003C
-#define SCC_RS_CTLSTS(base) ((base) + SCC_RS_CTLSTS_OFFS)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#define USBH_BASE 0x00080000
-
-/* Relative offsets of the register adresses */
-
-#define USBH_CAPLENGTH_OFFS 0x00000100
-#define USBH_CAPLENGTH(base) ((base) + USBH_CAPLENGTH_OFFS)
-#define USBH_USBCMD_OFFS 0x00000140
-#define USBH_USBCMD(base) ((base) + USBH_USBCMD_OFFS)
-#define USBH_BURSTSIZE_OFFS 0x00000160
-#define USBH_BURSTSIZE(base) ((base) + USBH_BURSTSIZE_OFFS)
-#define USBH_USBMODE_OFFS 0x000001A8
-#define USBH_USBMODE(base) ((base) + USBH_USBMODE_OFFS)
-#define USBH_USBHMISC_OFFS 0x00000200
-#define USBH_USBHMISC(base) ((base) + USBH_USBHMISC_OFFS)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#define WDT_BASE 0x000b0000
-#define WDT_CR_OFFS 0x00000000
-#define WDT_CR(base) ((base) + WDT_CR_OFFS)
-#define WDT_TORR_OFFS 0x00000004
-#define WDT_TORR(base) ((base) + WDT_TORR_OFFS)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#ifndef _REG_EBI_PREMIUM_H_
-#define _REG_EBI_PREMIUM_H_
-
-#define EBI_BASE 0x00000000
-
-/* Relative offsets of the register adresses */
-
-#define EBI_CPU_IO_ACCS_OFFS 0x00000000
-#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
-#define EBI_IO_ACCS_DATA_OFFS 0x00000004
-#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
-#define EBI_CPU_IO_ACCS2_OFFS 0x00000008
-#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS)
-#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C
-#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS)
-#define EBI_CTRL_OFFS 0x00000010
-#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
-#define EBI_IRQ_MASK_OFFS 0x00000018
-#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
-#define EBI_IRQ_MASK2_OFFS 0x0000001C
-#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS)
-#define EBI_TAG1_SYS_ID_OFFS 0x00000030
-#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
-#define EBI_TAG2_SYS_ID_OFFS 0x00000040
-#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
-#define EBI_TAG3_SYS_ID_OFFS 0x00000050
-#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
-#define EBI_TAG4_SYS_ID_OFFS 0x00000060
-#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
-#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
-#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
-#define EBI_STATUS_OFFS 0x00000080
-#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
-#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
-#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
-#define EBI_SIG_LEVEL_OFFS 0x00000088
-#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
-#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
-#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
-#define EBI_CRC_GEN_OFFS 0x00000090
-#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS)
-#define EBI_EXT_ADDR_OFFS 0x000000A0
-#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
-#define EBI_IRQ_STATUS_OFFS 0x000000B0
-#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
-#define EBI_IRQ_STATUS2_OFFS 0x000000B4
-#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS)
-#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0
-#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
-#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4
-#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
-#define EBI_ECC0_OFFS 0x000000D0
-#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS)
-#define EBI_ECC1_OFFS 0x000000D4
-#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS)
-#define EBI_ECC2_OFFS 0x000000D8
-#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS)
-#define EBI_ECC3_OFFS 0x000000DC
-#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS)
-#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
-#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
-#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
-#define EBI_DEV1_CONFIG1_OFFS 0x00000108
-#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
-#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
-#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
-#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
-#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
-#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
-#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
-#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
-#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
-#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
-#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
-#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120
-#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
-#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
-#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
-#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
-#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
-#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
-#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
-#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
-#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
-#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
-#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
-#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
-#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
-#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
-#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
-#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
-#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
-#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148
-#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
-#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C
-#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
-#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
-#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
-#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
-#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
-#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
-#define EBI_DEV2_CONFIG1_OFFS 0x00000208
-#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
-#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
-#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
-#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
-#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
-#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
-#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
-#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
-#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
-#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
-#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
-#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220
-#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
-#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
-#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
-#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
-#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
-#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
-#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
-#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
-#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
-#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
-#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
-#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
-#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
-#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
-#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
-#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
-#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
-#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248
-#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
-#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C
-#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
-#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
-#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
-#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
-#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
-#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
-#define EBI_DEV3_CONFIG1_OFFS 0x00000308
-#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
-#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
-#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
-#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
-#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
-#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
-#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
-#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
-#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
-#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
-#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
-#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320
-#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
-#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
-#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
-#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
-#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
-#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
-#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
-#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
-#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
-#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
-#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
-#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
-#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
-#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
-#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
-#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
-#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
-#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348
-#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
-#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C
-#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
-#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
-#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
-#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
-#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
-#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
-#define EBI_DEV4_CONFIG1_OFFS 0x00000408
-#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
-#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
-#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
-#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
-#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
-#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
-#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
-#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
-#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
-#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
-#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
-#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420
-#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
-#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
-#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
-#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
-#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
-#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
-#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
-#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
-#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
-#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
-#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
-#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
-#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
-#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
-#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
-#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
-#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
-#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448
-#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
-#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C
-#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
-#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
-#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
-#define EBI_INTERLEAVE_CNT_OFFS 0x00000900
-#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS)
-#define EBI_CNT_FL_PROGR_OFFS 0x00000904
-#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
-#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
-#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
-#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
-#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
-#define EBI_CNT_ACK_OFFS 0x00000918
-#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
-#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
-#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
-#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
-#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
-#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
-#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
-#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
-#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
-#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
-#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
-#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
-#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
-#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
-#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
-#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
-#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
-#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
-#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
-#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
-#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
-#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
-#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
-#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
-#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
-#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
-#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
-#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
-#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
-#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
-#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#define DCGU_BASE 0x0004c000
-#define DCGU_EN_WDT_RESET_OFFS 0x000000FC
-#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS)
-
-/* The magic value to write in order to activate the WDT */
-#define DCGU_MAGIC_WDT 0x1909
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- *
- * Copyright (C) 2006 Micronas GmbH
- */
-
-#ifndef _REG_EBI_PLATINUMAVC_H_
-#define _REG_EBI_PLATINUMAVC_H_
-
-#define EBI_BASE 0x00014000
-
-/* Relative offsets of the register adresses */
-
-#define EBI_CPU_IO_ACCS_OFFS 0x00000000
-#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
-#define EBI_IO_ACCS_DATA_OFFS 0x00000004
-#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
-#define EBI_CPU_IO_ACCS2_OFFS 0x00000008
-#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS)
-#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C
-#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS)
-#define EBI_CTRL_OFFS 0x00000010
-#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
-#define EBI_IRQ_MASK_OFFS 0x00000018
-#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
-#define EBI_IRQ_MASK2_OFFS 0x0000001C
-#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS)
-#define EBI_TAG1_SYS_ID_OFFS 0x00000030
-#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
-#define EBI_TAG2_SYS_ID_OFFS 0x00000040
-#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
-#define EBI_TAG3_SYS_ID_OFFS 0x00000050
-#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
-#define EBI_TAG4_SYS_ID_OFFS 0x00000060
-#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
-#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
-#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
-#define EBI_STATUS_OFFS 0x00000080
-#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
-#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
-#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
-#define EBI_SIG_LEVEL_OFFS 0x00000088
-#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
-#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
-#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
-#define EBI_CRC_GEN_OFFS 0x00000090
-#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS)
-#define EBI_EXT_ADDR_OFFS 0x000000A0
-#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
-#define EBI_IRQ_STATUS_OFFS 0x000000B0
-#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
-#define EBI_IRQ_STATUS2_OFFS 0x000000B4
-#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS)
-#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0
-#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
-#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4
-#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
-#define EBI_ECC0_OFFS 0x000000D0
-#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS)
-#define EBI_ECC1_OFFS 0x000000D4
-#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS)
-#define EBI_ECC2_OFFS 0x000000D8
-#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS)
-#define EBI_ECC3_OFFS 0x000000DC
-#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS)
-#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
-#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
-#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
-#define EBI_DEV1_CONFIG1_OFFS 0x00000108
-#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
-#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
-#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
-#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
-#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
-#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
-#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
-#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
-#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
-#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
-#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
-#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120
-#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
-#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
-#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
-#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
-#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
-#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
-#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
-#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
-#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
-#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
-#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
-#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
-#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
-#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
-#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
-#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
-#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
-#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148
-#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
-#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C
-#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
-#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
-#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
-#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
-#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
-#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
-#define EBI_DEV2_CONFIG1_OFFS 0x00000208
-#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
-#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
-#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
-#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
-#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
-#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
-#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
-#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
-#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
-#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
-#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
-#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220
-#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
-#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
-#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
-#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
-#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
-#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
-#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
-#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
-#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
-#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
-#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
-#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
-#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
-#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
-#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
-#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
-#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
-#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248
-#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
-#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C
-#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
-#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
-#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
-#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
-#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
-#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
-#define EBI_DEV3_CONFIG1_OFFS 0x00000308
-#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
-#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
-#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
-#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
-#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
-#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
-#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
-#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
-#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
-#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
-#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
-#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320
-#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
-#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
-#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
-#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
-#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
-#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
-#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
-#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
-#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
-#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
-#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
-#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
-#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
-#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
-#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
-#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
-#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
-#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348
-#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
-#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C
-#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
-#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
-#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
-#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
-#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
-#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
-#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
-#define EBI_DEV4_CONFIG1_OFFS 0x00000408
-#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
-#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
-#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
-#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
-#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
-#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
-#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
-#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
-#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
-#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
-#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
-#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420
-#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
-#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
-#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
-#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
-#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
-#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
-#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
-#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
-#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
-#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
-#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
-#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
-#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
-#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
-#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
-#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
-#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
-#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
-#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
-#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448
-#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
-#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C
-#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
-#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
-#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
-#define EBI_INTERLEAVE_CNT_OFFS 0x00000900
-#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS)
-#define EBI_CNT_FL_PROGR_OFFS 0x00000904
-#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
-#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
-#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
-#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
-#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
-#define EBI_CNT_ACK_OFFS 0x00000918
-#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
-#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
-#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
-#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
-#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
-#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
-#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
-#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
-#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
-#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
-#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
-#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
-#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
-#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
-#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
-#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
-#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
-#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
-#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
-#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
-#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
-#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
-#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
-#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
-#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
-#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
-#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
-#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
-#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
-#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
-#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#define GPIO1_BASE 0x00044000
-#define GPIO2_BASE 0x00048000
-
-/* Instances */
-#define GPIO_INSTANCES 2
-
-/* Relative offsets of the register adresses */
-#define GPIO_SWPORTA_DR_OFFS 0x00000000
-#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS)
-#define GPIO_SWPORTA_DDR_OFFS 0x00000004
-#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS)
-#define GPIO_EXT_PORTA_OFFS 0x00000050
-#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-#define WDT_BASE 0x00040000
-#define WDT_CR_OFFS 0x00000000
-#define WDT_CR(base) ((base) + WDT_CR_OFFS)
-#define WDT_TORR_OFFS 0x00000004
-#define WDT_TORR(base) ((base) + WDT_TORR_OFFS)
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_WDT=y
CONFIG_WDT_SP805=y
CONFIG_RSA=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_WDT=y
CONFIG_WDT_SP805=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_WDT=y
CONFIG_WDT_SP805=y
CONFIG_RSA=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_WDT=y
CONFIG_WDT_SP805=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NXP_ESBC=y
CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_ENV_OFFSET=0x500000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_NXP_ESBC=y
CONFIG_EMC2305=y
CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_EMC2305=y
CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_ENV_OFFSET=0x500000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PLATINUM=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="$ "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xB0040000
-CONFIG_ENV_ADDR_REDUND=0xB0050000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x00000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PLATINUM=y
-CONFIG_VCT_ONENAND=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="$ "
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_ONENAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_ENV_IS_IN_ONENAND=y
-CONFIG_ENV_ADDR=0x20000
-CONFIG_MTD_DEVICE=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x00000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PLATINUM=y
-CONFIG_VCT_ONENAND=y
-CONFIG_VCT_SMALL_IMAGE=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="$ "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_ONENAND=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_ONENAND=y
-CONFIG_ENV_ADDR=0x20000
-# CONFIG_NET is not set
-CONFIG_MTD_DEVICE=y
-CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PLATINUM=y
-CONFIG_VCT_SMALL_IMAGE=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="$ "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_MISC is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xB0040000
-CONFIG_ENV_ADDR_REDUND=0xB0050000
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PLATINUMAVC=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="VCT# "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xB0040000
-CONFIG_ENV_ADDR_REDUND=0xB0050000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_NS16550=y
-# CONFIG_REGEX is not set
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PLATINUMAVC=y
-CONFIG_VCT_ONENAND=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="$ "
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_ONENAND=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_ONENAND=y
-CONFIG_ENV_ADDR=0x20000
-CONFIG_MTD_DEVICE=y
-CONFIG_SYS_NS16550=y
-# CONFIG_REGEX is not set
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PLATINUMAVC=y
-CONFIG_VCT_ONENAND=y
-CONFIG_VCT_SMALL_IMAGE=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="$ "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_ONENAND=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_ONENAND=y
-CONFIG_ENV_ADDR=0x20000
-# CONFIG_NET is not set
-CONFIG_MTD_DEVICE=y
-CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PLATINUMAVC=y
-CONFIG_VCT_SMALL_IMAGE=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="$ "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_MISC is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xB0040000
-CONFIG_ENV_ADDR_REDUND=0xB0050000
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PREMIUM=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="$ "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xB0040000
-CONFIG_ENV_ADDR_REDUND=0xB0050000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x00000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PREMIUM=y
-CONFIG_VCT_ONENAND=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="$ "
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_ONENAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_ENV_IS_IN_ONENAND=y
-CONFIG_ENV_ADDR=0x20000
-CONFIG_MTD_DEVICE=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x00000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PREMIUM=y
-CONFIG_VCT_ONENAND=y
-CONFIG_VCT_SMALL_IMAGE=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="$ "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_ONENAND=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_ONENAND=y
-CONFIG_ENV_ADDR=0x20000
-# CONFIG_NET is not set
-CONFIG_MTD_DEVICE=y
-CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_VCT=y
-CONFIG_VCT_PREMIUM=y
-CONFIG_VCT_SMALL_IMAGE=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="$ "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_MISC is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xB0040000
-CONFIG_ENV_ADDR_REDUND=0xB0050000
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_NS16550=y
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"bootm $load_addr#$board\0" \
- "qspi_bootcmd=echo Trying load from qspi..;" \
+ "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size; env exists secureboot " \
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
"installer=load usb 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"bootm $load_addr#$board\0" \
- "qspi_bootcmd=echo Trying load from qspi..;" \
+ "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size && bootm $load_addr#$board\0"
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"bootm $load_addr#$board\0" \
- "qspi_bootcmd=echo Trying load from qspi..;" \
+ "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size; env exists secureboot " \
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
"bootm $load_addr#$board\0" \
- "sd_bootcmd=echo Trying load from sd card..;" \
+ "sd_bootcmd=pfe stop; echo Trying load from sd card..;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"bootm $load_addr#$board\0" \
- "qspi_bootcmd=echo Trying load from qspi..;" \
+ "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size; env exists secureboot " \
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
func(USB, usb, 0)
#include <config_distro_bootcmd.h>
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
- "sd_bootcmd=echo Trying load from SD ..;" \
+ "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
+ "sf probe 0:0 && sf read $load_addr " \
+ "$kernel_start $kernel_size ; env exists secureboot &&" \
+ "sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ " bootm $load_addr#$board\0" \
+ "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
+ "sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \
+ "&& hdp load $load_addr 0x2000\0" \
+ "sd_bootcmd=echo Trying load from SD ...;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && " \
"env exists secureboot && mmc read $kernelheader_addr_r " \
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0" \
+ "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \
+ "mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
+ "&& hdp load $load_addr 0x2000\0" \
"emmc_bootcmd=echo Trying load from EMMC ..;" \
"mmcinfo; mmc dev 1; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && " \
"env exists secureboot && mmc read $kernelheader_addr_r " \
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
" && esbc_validate ${kernelheader_addr_r};" \
- "bootm $load_addr#$board\0"
+ "bootm $load_addr#$board\0" \
+ "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \
+ "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
+ "&& hdp load $load_addr 0x2000\0"
#undef CONFIG_BOOTCOMMAND
+#define XSPI_NOR_BOOTCOMMAND \
+ "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;;"
#define SD_BOOTCOMMAND \
- "run distro_bootcmd;run sd_bootcmd; " \
+ "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#define SD2_BOOTCOMMAND \
+ "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
"env exists secureboot && esbc_halt;"
/* Monitor Command Prompt */
"source ${scriptaddr}\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
- "$kernel_addr $kernel_size; env exists secureboot " \
- "&& sf read $kernelheader_addr_r $kernelheader_addr " \
+ "$kernel_start $kernel_size; env exists secureboot " \
+ "&& sf read $kernelheader_addr_r $kernelheader_start " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
"bootm $load_addr#$board\0" \
"nor_bootcmd=echo Trying load from nor..;" \
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
- */
-
-/*
- * This file contains the configuration parameters for the VCT board
- * family:
- *
- * vct_premium
- * vct_premium_small
- * vct_premium_onenand
- * vct_premium_onenand_small
- * vct_platinum
- * vct_platinum_small
- * vct_platinum_onenand
- * vct_platinum_onenand_small
- * vct_platinumavc
- * vct_platinumavc_small
- * vct_platinumavc_onenand
- * vct_platinumavc_onenand_small
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
-
-#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_SYS_MALLOC_LEN (1 << 20)
-#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10)
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-
-#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
-#define CONFIG_VCT_NOR
-#endif
-
-/*
- * UART
- */
-#ifdef CONFIG_VCT_PLATINUMAVC
-#define UART_1_BASE 0xBDC30000
-#else
-#define UART_1_BASE 0xBF89C000
-#endif
-
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 UART_1_BASE
-#define CONFIG_SYS_NS16550_CLK 921600
-
-/*
- * SDRAM
- */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_MBYTES_SDRAM 128
-#define CONFIG_SYS_MEMTEST_START 0x80200000
-#define CONFIG_SYS_MEMTEST_END 0x80400000
-#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
-
-#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
-#define CONFIG_NET_RETRY_COUNT 20
-#endif
-
-/*
- * Commands
- */
-#if defined(CONFIG_CMD_USB)
-
-/*
- * USB/EHCI
- */
-#define CONFIG_USB_EHCI_VCT /* on VCT platform */
-#define CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
-#endif /* CONFIG_CMD_USB */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * FLASH and environment organization
- */
-#if defined(CONFIG_VCT_NOR)
-#define CONFIG_FLASH_NOT_MEM_MAPPED
-
-/*
- * We need special accessor functions for the CFI FLASH driver. This
- * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
- */
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-
-/*
- * For the non-memory-mapped NOR FLASH, we need to define the
- * NOR FLASH area. This can't be detected via the addr2info()
- * function, since we check for flash access in the very early
- * U-Boot code, before the NOR FLASH is detected.
- */
-#define CONFIG_FLASH_BASE 0xb0000000
-#define CONFIG_FLASH_END 0xbfffffff
-
-/*
- * CFI driver settings
- */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
-
-#define CONFIG_SYS_FLASH_BASE 0xb0000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-/* Address and size of Redundant Environment Sector */
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-#endif /* CONFIG_VCT_NOR */
-
-#if defined(CONFIG_VCT_ONENAND)
-#define CONFIG_USE_ONENAND_BOARD_INIT
-#define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#endif /* CONFIG_VCT_ONENAND */
-
-/*
- * I2C/EEPROM
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define CONFIG_SYS_GPIO_I2C_SCL 11
-#define CONFIG_SYS_GPIO_I2C_SDA 10
-
-#ifndef __ASSEMBLY__
-int vct_gpio_dir(int pin, int dir);
-void vct_gpio_set(int pin, int val);
-int vct_gpio_get(int pin);
-#endif
-
-#define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
-#define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
-#define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
-#define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
-#define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
-#define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-/* CAT24WC32 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
- /* 32 byte page write mode using*/
- /* last 5 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_BOOTCOMMAND "run test3"
-
-/*
- * UBI configuration
- */
-
-/*
- * We need a small, stripped down image to fit into the first 128k OneNAND
- * erase block (gzipped). This image only needs basic commands for FLASH
- * (NOR/OneNAND) usage and Linux kernel booting.
- */
-#if defined(CONFIG_VCT_SMALL_IMAGE)
-#undef CONFIG_SYS_I2C_SOFT
-#undef CONFIG_SOURCE
-#undef CONFIG_TIMESTAMP
-#endif /* CONFIG_VCT_SMALL_IMAGE */
-
-#endif /* __CONFIG_H */
git.openpandora.org / pandora-u-boot.git / commitdiff