# Grab our configured image. The source for this is found at:
# https://gitlab.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:bionic-20200112-17Jan2020
+image: trini/u-boot-gitlab-ci-runner:bionic-20200112-07Feb2020
# We run some tests in different order, to catch some failures quicker.
stages:
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
- grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- - mkdir ~/grub2-arm
- - ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di )
- - mkdir ~/grub2-arm64
- - ( cd ~/grub2-arm64; wget -O - http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm | rpm2cpio | cpio -di )
+ - cp /opt/grub/grubriscv64.efi ~/grub_riscv64.efi
+ - cp /opt/grub/grubaa64.efi ~/grub_arm64.efi
+ - cp /opt/grub/grubarm.efi ~/grub_arm.efi
after_script:
- - rm -rf ~/grub2* /tmp/uboot-test-hooks /tmp/venv
+ - rm -rf /tmp/uboot-test-hooks /tmp/venv
script:
# From buildman, exit code 129 means warnings only. If we've been asked to
# use clang only do one configuration.
- if [[ "${BUILDMAN}" != "" ]]; then
ret=0;
- tools/buildman/buildman -o /tmp -P -E ${BUILDMAN} ${OVERRIDE}|| ret=$?;
+ NO_SDL=1 tools/buildman/buildman -o /tmp -P -E ${BUILDMAN}
+ ${OVERRIDE}|| ret=$?;
if [[ $ret -ne 0 && $ret -ne 129 ]]; then
tools/buildman/buildman -o /tmp -sdeP ${BUILDMAN};
exit $ret;
export UBOOT_TRAVIS_BUILD_DIR=/tmp/.bm-work/sandbox_spl;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
- ./tools/buildman/buildman -o /tmp -P sandbox_spl;
+ NO_SDL=1 ./tools/buildman/buildman -o /tmp -P sandbox_spl;
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
./tools/buildman/buildman -t;
./tools/dtoc/dtoc -t;
<&gpio_b 9 0xc 3 2 1>;
int-value = <1234>;
uint-value = <(-1234)>;
+ interrupts-extended = <&irq 3 0>;
};
junk {
vss-microvolts = <0>;
};
- irq {
+ irq: irq {
compatible = "sandbox,irq";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
lcd {
chosen {
#address-cells = <1>;
#size-cells = <1>;
+ setting = "sunrise ohoka";
+ other-node = "/some-bus/c-test@5";
+ int-values = <0x1937 72993>;
chosen-test {
compatible = "denx,u-boot-fdt-test";
reg = <9 1>;
#define PCI_EA_BAR2_MAGIC 0x72727272
#define PCI_EA_BAR4_MAGIC 0x74747474
+enum {
+ SANDBOX_IRQN_PEND = 1, /* Interrupt number for 'pending' test */
+};
+
/* System controller driver data */
enum {
SYSCON0 = 32,
*/
int sandbox_get_setup_called(struct udevice *dev);
+ /**
+ * sandbox_get_sound_active() - Returns whether sound play is in progress
+ *
+ * @return true if active, false if not
+ */
+ int sandbox_get_sound_active(struct udevice *dev);
+
/**
* sandbox_get_sound_sum() - Read back the sum of the sound data so far
*
#include <binman.h>
#include <dm.h>
#include <irq.h>
+ #include <malloc.h>
#include <asm/intel_pinctrl.h>
#include <asm/io.h>
#include <asm/intel_regs.h>
#define HIDE_BIT BIT(0)
#define INTEL_GSPI_MAX 3
-#define INTEL_I2C_DEV_MAX 8
#define MAX_USB2_PORTS 8
enum {
CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
};
-enum i2c_speed {
- I2C_SPEED_STANDARD = 100000,
- I2C_SPEED_FAST = 400000,
- I2C_SPEED_FAST_PLUS = 1000000,
- I2C_SPEED_HIGH = 3400000,
- I2C_SPEED_FAST_ULTRA = 5000000,
-};
-
-/*
- * Timing values are in units of clock period, with the clock speed
- * provided by the SOC
- *
- * TODO(sjg@chromium.org): Connect this up to the I2C driver
- */
-struct dw_i2c_speed_config {
- enum i2c_speed speed;
- /* SCL high and low period count */
- u16 scl_lcnt;
- u16 scl_hcnt;
- /*
- * SDA hold time should be 300ns in standard and fast modes
- * and long enough for deterministic logic level change in
- * fast-plus and high speed modes.
- *
- * [15:0] SDA TX Hold Time
- * [23:16] SDA RX Hold Time
- */
- u32 sda_hold;
-};
-
/* Serial IRQ control. SERIRQ_QUIET is the default (0) */
enum serirq_mode {
SERIRQ_QUIET,
SERIRQ_OFF,
};
-/*
- * This I2C controller has support for 3 independent speed configs but can
- * support both FAST_PLUS and HIGH speeds through the same set of speed
- * config registers. These are treated separately so the speed config values
- * can be provided via ACPI to the OS.
- */
-#define DW_I2C_SPEED_CONFIG_COUNT 4
-
-struct dw_i2c_bus_config {
- /* Bus should be enabled in TPL with temporary base */
- int early_init;
- /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
- enum i2c_speed speed;
- /*
- * If rise_time_ns is non-zero the calculations for lcnt and hcnt
- * registers take into account the times of the bus. However, if
- * there is a match in speed_config those register values take
- * precedence
- */
- int rise_time_ns;
- int fall_time_ns;
- int data_hold_time_ns;
- /* Specific bus speed configuration */
- struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT];
-};
-
struct gspi_cfg {
/* Bus speed in MHz */
u32 speed_mhz;
struct soc_intel_common_config {
int chipset_lockdown;
struct gspi_cfg gspi[INTEL_GSPI_MAX];
- struct dw_i2c_bus_config i2c[INTEL_I2C_DEV_MAX];
};
enum pnp_settings {
struct udevice *itss;
int ret;
- ret = uclass_first_device_err(UCLASS_IRQ, &itss);
+ ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
if (ret)
return log_msg_ret("no itss", ret);
/*
if (ret)
return ret;
- ret = uclass_first_device_err(UCLASS_IRQ, &itss);
+ ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
if (ret)
return log_msg_ret("no itss", ret);
/* Restore GPIO IRQ polarities back to previous settings */
#include <dm.h>
#include <dt-structs.h>
#include <irq.h>
+ #include <malloc.h>
#include <p2sb.h>
#include <spl.h>
#include <asm/itss.h>
return -ENOENT;
}
+static int itss_bind(struct udevice *dev)
+{
+ /* This is not set with of-platdata, so set it manually */
+ if (CONFIG_IS_ENABLED(OF_PLATDATA))
+ dev->driver_data = X86_IRQT_ITSS;
+
+ return 0;
+}
+
static int itss_ofdata_to_platdata(struct udevice *dev)
{
struct itss_priv *priv = dev_get_priv(dev);
};
static const struct udevice_id itss_ids[] = {
- { .compatible = "intel,itss"},
+ { .compatible = "intel,itss", .data = X86_IRQT_ITSS },
{ }
};
.id = UCLASS_IRQ,
.of_match = itss_ids,
.ops = &itss_ops,
+ .bind = itss_bind,
.ofdata_to_platdata = itss_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct itss_platdata),
.priv_auto_alloc_size = sizeof(struct itss_priv),
*/
#include "vpd_reader.h"
+ #include <malloc.h>
#include <i2c.h>
#include <linux/bch.h>
#include <stdlib.h>
+#include <dm/uclass.h>
+#include <i2c_eeprom.h>
+#include <hexdump.h>
/* BCH configuration */
int (*process_block)(struct vpd_cache *, u8 id, u8 version,
u8 type, size_t size, u8 const *data))
{
- static const size_t size = CONFIG_SYS_VPD_EEPROM_SIZE;
-
- int res;
+ struct udevice *dev;
+ int ret;
u8 *data;
- unsigned int current_i2c_bus = i2c_get_bus_num();
+ int size;
+
+ ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd", &dev);
+ if (ret)
+ return ret;
- res = i2c_set_bus_num(CONFIG_SYS_VPD_EEPROM_I2C_BUS);
- if (res < 0)
- return res;
+ size = i2c_eeprom_size(dev);
+ if (size < 0) {
+ printf("Unable to get size of eeprom: %d\n", ret);
+ return ret;
+ }
data = malloc(size);
if (!data)
return -ENOMEM;
- res = i2c_read(CONFIG_SYS_VPD_EEPROM_I2C_ADDR, 0,
- CONFIG_SYS_VPD_EEPROM_I2C_ADDR_LEN,
- data, size);
- if (res == 0)
- res = vpd_reader(size, data, cache, process_block);
+ ret = i2c_eeprom_read(dev, 0, data, size);
+ if (ret) {
+ free(data);
+ return ret;
+ }
+
+ ret = vpd_reader(size, data, cache, process_block);
free(data);
- i2c_set_bus_num(current_i2c_bus);
- return res;
+ return ret;
}
#include <command.h>
#include <errno.h>
#include <dm.h>
+ #include <malloc.h>
#include <asm/gpio.h>
+ #include <linux/err.h>
__weak int name_to_gpio(const char *name)
{
gpio_direction_output(gpio, value);
}
printf("gpio: pin %s (gpio %u) value is ", str_gpio, gpio);
- if (IS_ERR_VALUE(value))
+
+ if (IS_ERR_VALUE(value)) {
printf("unknown (ret=%d)\n", value);
- else
+ goto err;
+ } else {
printf("%d\n", value);
+ }
+
if (sub_cmd != GPIOC_INPUT && !IS_ERR_VALUE(value)) {
int nval = gpio_get_value(gpio);
- if (IS_ERR_VALUE(nval))
+ if (IS_ERR_VALUE(nval)) {
printf(" Warning: no access to GPIO output value\n");
- else if (nval != value)
+ goto err;
+ } else if (nval != value) {
printf(" Warning: value of pin is still %d\n", nval);
+ goto err;
+ }
}
if (ret != -EBUSY)
gpio_free(gpio);
- return value;
+ return CMD_RET_SUCCESS;
+
+err:
+ if (ret != -EBUSY)
+ gpio_free(gpio);
+ return CMD_RET_FAILURE;
}
U_BOOT_CMD(gpio, 4, 0, do_gpio,
#include <errno.h>
#include <regmap.h>
#include <dm/device-internal.h>
+ #include <dm/device_compat.h>
#include <dm/lists.h>
#include <dm/root.h>
#include <linux/err.h>
int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
{
- struct udevice *dev;
- struct uclass *uc;
int ret;
*devp = NULL;
- ret = uclass_get(UCLASS_SYSCON, &uc);
+
+ ret = uclass_first_device_drvdata(UCLASS_SYSCON, driver_data, devp);
if (ret)
- return ret;
- uclass_foreach_dev(dev, uc) {
- if (dev->driver_data == driver_data) {
- *devp = dev;
- return device_probe(dev);
- }
- }
+ return log_msg_ret("find", ret);
- return -ENODEV;
+ return 0;
}
struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data)
return -ENODEV;
}
- #if !CONFIG_IS_ENABLED(OF_CONTROL) || \
- CONFIG_IS_ENABLED(OF_PLATDATA) || \
- CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
int uclass_find_next_free_req_seq(enum uclass_id id)
{
struct uclass *uc;
return max + 1;
}
- #endif
int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq,
bool find_req_seq, struct udevice **devp)
return device_probe(*devp);
}
+int uclass_first_device_drvdata(enum uclass_id id, ulong driver_data,
+ struct udevice **devp)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+
+ uclass_id_foreach_dev(id, dev, uc) {
+ if (dev_get_driver_data(dev) == driver_data) {
+ *devp = dev;
+
+ return device_probe(dev);
+ }
+ }
+
+ return -ENODEV;
+}
+
int uclass_bind_device(struct udevice *dev)
{
struct uclass *uc;
#include <asm/arch/sdram.h>
#include <asm/arch/system_manager.h>
#include <asm/io.h>
+ #include <dm/device_compat.h>
#include "sequencer.h"
debug("Configuring DRAMODT\n");
writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
- debug("Configuring EXTRATIME1\n");
- writel(cfg->extratime1, &sdr_ctrl->extratime1);
+ if (dram_is_ddr(3)) {
+ debug("Configuring EXTRATIME1\n");
+ writel(cfg->extratime1, &sdr_ctrl->extratime1);
+ }
}
/**
#endif
#include <asm/arch/gpio.h>
#include <asm/arch-tegra/tegra_i2c.h>
+ #include <linux/err.h>
enum i2c_type {
TYPE_114,
int tegra_i2c_get_dvc_bus(struct udevice **busp)
{
- struct udevice *bus;
-
- for (uclass_first_device(UCLASS_I2C, &bus);
- bus;
- uclass_next_device(&bus)) {
- if (dev_get_driver_data(bus) == TYPE_DVC) {
- *busp = bus;
- return 0;
- }
- }
-
- return -ENODEV;
+ return uclass_first_device_drvdata(UCLASS_I2C, TYPE_DVC, busp);
}
static const struct dm_i2c_ops tegra_i2c_ops = {
#include <wait_bit.h>
#include <asm/gpio.h>
#include <asm/io.h>
+ #include <dm/device_compat.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/mdio.h>
enum mtk_soc {
SOC_MT7623,
- SOC_MT7629
+ SOC_MT7629,
+ SOC_MT7622
};
struct mtk_eth_priv {
void __iomem *fe_base;
void __iomem *gmac_base;
void __iomem *ethsys_base;
+ void __iomem *sgmii_base;
struct mii_dev *mdio_bus;
int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
return 0;
}
+static void mtk_sgmii_init(struct mtk_eth_priv *priv)
+{
+ /* Set SGMII GEN2 speed(2.5G) */
+ clrsetbits_le32(priv->sgmii_base + SGMSYS_GEN2_SPEED,
+ SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
+
+ /* Disable SGMII AN */
+ clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
+ SGMII_AN_ENABLE, 0);
+
+ /* SGMII force mode setting */
+ writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
+
+ /* Release PHYA power down state */
+ clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
+ SGMII_PHYA_PWD, 0);
+}
+
static void mtk_mac_init(struct mtk_eth_priv *priv)
{
int i, ge_mode = 0;
switch (priv->phy_interface) {
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII:
+ ge_mode = GE_MODE_RGMII;
+ break;
case PHY_INTERFACE_MODE_SGMII:
ge_mode = GE_MODE_RGMII;
+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
+ SYSCFG0_SGMII_SEL(priv->gmac_id));
+ mtk_sgmii_init(priv);
break;
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc));
memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE);
- flush_dcache_range((u32)pkt_base, (u32)(pkt_base + TOTAL_PKT_BUF_SIZE));
+ flush_dcache_range((ulong)pkt_base,
+ (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE));
priv->rx_dma_owner_idx0 = 0;
priv->tx_cpu_owner_idx0 = 0;
pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0);
memcpy(pkt_base, packet, length);
- flush_dcache_range((u32)pkt_base, (u32)pkt_base +
+ flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
roundup(length, ARCH_DMA_MINALIGN));
priv->tx_ring_noc[idx].txd_info2.SDL0 = length;
length = priv->rx_ring_noc[idx].rxd_info2.PLEN0;
pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0);
- invalidate_dcache_range((u32)pkt_base, (u32)pkt_base +
+ invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base +
roundup(length, ARCH_DMA_MINALIGN));
if (packetp)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct mtk_eth_priv *priv = dev_get_priv(dev);
- u32 iobase = pdata->iobase;
+ ulong iobase = pdata->iobase;
int ret;
/* Frame Engine Register Base */
}
}
+ if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ /* get corresponding sgmii phandle */
+ ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
+ NULL, 0, 0, &args);
+ if (ret)
+ return ret;
+
+ regmap = syscon_node_to_regmap(args.node);
+
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ priv->sgmii_base = regmap_get_range(regmap, 0);
+
+ if (!priv->sgmii_base) {
+ dev_err(dev, "Unable to find sgmii\n");
+ return -ENODEV;
+ }
+ }
+
/* check for switch first, otherwise phy will be used */
priv->sw = SW_NONE;
priv->switch_init = NULL;
static const struct udevice_id mtk_eth_ids[] = {
{ .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
{ .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
+ { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 },
{}
};
#include <common.h>
#include <dm.h>
#include <irq.h>
+ #include <malloc.h>
#include <p2sb.h>
#include <spl.h>
#include <asm-generic/gpio.h>
#include <asm/itss.h>
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>
+ #include <linux/err.h>
#define GPIO_DW_SIZE(x) (sizeof(u32) * (x))
#define PAD_CFG_OFFSET(x, dw_num) ((x) + GPIO_DW_SIZE(dw_num))
log_err("Cannot find community for pid %d\n", pplat->pid);
return -EDOM;
}
- ret = uclass_first_device_err(UCLASS_IRQ, &priv->itss);
+ ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss);
if (ret)
return log_msg_ret("Cannot find ITSS", ret);
priv->comm = comm;
#include <common.h>
#include <dm.h>
+ #include <malloc.h>
#include <dm/lists.h>
#include <dm/of_access.h>
#include <env.h>
#include <reset-uclass.h>
+#include <wait_bit.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
int offset = id % (reg_width * BITS_PER_BYTE);
clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
- return 0;
+
+ return wait_for_bit_le32(data->modrst_base + (bank * BANK_INCREMENT),
+ BIT(offset),
+ false, 500, false);
}
static int socfpga_reset_request(struct reset_ctl *reset_ctl)
static const struct reset_ops socfpga_reset_ops = {
.request = socfpga_reset_request,
- .free = socfpga_reset_free,
+ .rfree = socfpga_reset_free,
.rst_assert = socfpga_reset_assert,
.rst_deassert = socfpga_reset_deassert,
};
if TPM_V2
+config TPM2_CR50_I2C
+ bool "Enable support for Google cr50 TPM"
+ depends on DM_I2C
+ help
+ Cr50 is an implementation of a TPM on Google's H1 security chip.
+ This uses the same open-source firmware as the Chromium OS EC.
+ While Cr50 has other features, its primary role is as the root of
+ trust for a device, It operates like a TPM and can be used with
+ verified boot. Cr50 is used on recent Chromebooks (since 2017).
+
config TPM2_TIS_SANDBOX
bool "Enable sandbox TPMv2.x driver"
depends on TPM_V2 && SANDBOX
to the device using the standard TPM Interface Specification (TIS)
protocol.
+ config TPM2_FTPM_TEE
+ bool "TEE based fTPM Interface"
+ depends on TEE && OPTEE && TPM_V2
+ help
+ This driver supports firmware TPM running in TEE.
+
endif # TPM_V2
endmenu
obj-$(CONFIG_TPM_ST33ZP24_I2C) += tpm_tis_st33zp24_i2c.o
obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o
+obj-$(CONFIG_TPM2_CR50_I2C) += cr50_i2c.o
obj-$(CONFIG_TPM2_TIS_SANDBOX) += tpm2_tis_sandbox.o
obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_spi.o
+ obj-$(CONFIG_TPM2_FTPM_TEE) += tpm2_ftpm_tee.o
#include <common.h>
#include <dm.h>
#include <env.h>
+ #include <dm/device_compat.h>
#include <linux/errno.h>
#include <malloc.h>
#include <video.h>
.bind = mxs_video_bind,
.probe = mxs_video_probe,
.remove = mxs_video_remove,
- .flags = DM_FLAG_PRE_RELOC,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
};
#endif /* ifndef CONFIG_DM_VIDEO */
#include <command.h>
#include <config.h>
#include <fat.h>
+ #include <malloc.h>
#include <asm/byteorder.h>
#include <part.h>
#include <linux/ctype.h>
newclust = get_fatent(mydata, endclust);
+ if (newclust != endclust + 1)
+ break;
if (IS_LAST_CLUST(newclust, mydata->fatsize))
break;
if (CHECK_CLUST(newclust, mydata->fatsize)) {
offset = 0;
else
offset = pos - cur_pos;
- wsize = min(cur_pos + actsize, filesize) - pos;
+ wsize = min_t(unsigned long long, actsize, filesize - cur_pos);
+ wsize -= offset;
+
if (get_set_cluster(mydata, curclust, offset,
buffer, wsize, &actsize)) {
printf("Error get-and-setting cluster\n");
if (filesize <= cur_pos)
break;
- /* CHECK: newclust = get_fatent(mydata, endclust); */
-
if (IS_LAST_CLUST(newclust, mydata->fatsize))
/* no more clusters */
break;
#include <dm/test.h>
#include <dm/root.h>
#include <dm/device-internal.h>
+ #include <dm/devres.h>
#include <dm/uclass-internal.h>
#include <dm/util.h>
#include <dm/lists.h>
}
DM_TEST(dm_test_first_next_device, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+/* Test iteration through devices in a uclass */
+static int dm_test_uclass_foreach(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int count;
+
+ count = 0;
+ uclass_id_foreach_dev(UCLASS_TEST_FDT, dev, uc)
+ count++;
+ ut_asserteq(8, count);
+
+ count = 0;
+ uclass_foreach_dev(dev, uc)
+ count++;
+ ut_asserteq(8, count);
+
+ return 0;
+}
+DM_TEST(dm_test_uclass_foreach, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
/**
* check_devices() - Check return values and pointers
*
return 0;
}
DM_TEST(dm_test_read_int, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test iteration through devices by drvdata */
+static int dm_test_uclass_drvdata(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_first_device_drvdata(UCLASS_TEST_FDT,
+ DM_TEST_TYPE_FIRST, &dev));
+ ut_asserteq_str("a-test", dev->name);
+
+ ut_assertok(uclass_first_device_drvdata(UCLASS_TEST_FDT,
+ DM_TEST_TYPE_SECOND, &dev));
+ ut_asserteq_str("d-test", dev->name);
+
+ ut_asserteq(-ENODEV, uclass_first_device_drvdata(UCLASS_TEST_FDT,
+ DM_TEST_TYPE_COUNT,
+ &dev));
+
+ return 0;
+}
+DM_TEST(dm_test_uclass_drvdata, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+ /* Test device_first_child_ofdata_err(), etc. */
+ static int dm_test_child_ofdata(struct unit_test_state *uts)
+ {
+ struct udevice *bus, *dev;
+ int count;
+
+ ut_assertok(uclass_first_device_err(UCLASS_TEST_BUS, &bus));
+ count = 0;
+ device_foreach_child_ofdata_to_platdata(dev, bus) {
+ ut_assert(dev->flags & DM_FLAG_PLATDATA_VALID);
+ ut_assert(!(dev->flags & DM_FLAG_ACTIVATED));
+ count++;
+ }
+ ut_asserteq(3, count);
+
+ return 0;
+ }
+ DM_TEST(dm_test_child_ofdata, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+ /* Test device_first_child_err(), etc. */
+ static int dm_test_first_child_probe(struct unit_test_state *uts)
+ {
+ struct udevice *bus, *dev;
+ int count;
+
+ ut_assertok(uclass_first_device_err(UCLASS_TEST_BUS, &bus));
+ count = 0;
+ device_foreach_child_probe(dev, bus) {
+ ut_assert(dev->flags & DM_FLAG_PLATDATA_VALID);
+ ut_assert(dev->flags & DM_FLAG_ACTIVATED);
+ count++;
+ }
+ ut_asserteq(3, count);
+
+ return 0;
+ }
+ DM_TEST(dm_test_first_child_probe, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
git.openpandora.org / pandora-u-boot.git / commitdiff