[PATCH] sky2: yukon-ec-u chipset initialization

Add more complete setup code for Yukon EC_U chipset.
Based on matching code in 8.31 code in SysKonnect vendor driver.

Signed-off-by: Stephen Hemminger <shemminger@osdl.org>

diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index bfeba5b..ce135b8 100644 (file)
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -232,7 +232,17 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
                        if (hw->ports > 1)
                                reg1 |= PCI_Y2_PHY2_COMA;
                }
+
+               if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
+                       pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
+                       pci_read_config_dword(hw->pdev, PCI_DEV_REG4, &reg1);
+                       reg1 &= P_ASPM_CONTROL_MSK;
+                       pci_write_config_dword(hw->pdev, PCI_DEV_REG4, reg1);
+                       pci_write_config_dword(hw->pdev, PCI_DEV_REG5, 0);
+               }
+
                pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
+
                break;
 
        case PCI_D3hot:
@@ -463,16 +473,31 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
                ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
        }
 
-       gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
+       if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
+               /* apply fixes in PHY AFE */
+               gm_phy_write(hw, port, 22, 255);
+               /* increase differential signal amplitude in 10BASE-T */
+               gm_phy_write(hw, port, 24, 0xaa99);
+               gm_phy_write(hw, port, 23, 0x2011);
 
-       if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
-               /* turn on 100 Mbps LED (LED_LINK100) */
-               ledover |= PHY_M_LED_MO_100(MO_LED_ON);
-       }
+               /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
+               gm_phy_write(hw, port, 24, 0xa204);
+               gm_phy_write(hw, port, 23, 0x2002);
 
-       if (ledover)
-               gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
+               /* set page register to 0 */
+               gm_phy_write(hw, port, 22, 0);
+       } else {
+               gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
 
+               if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
+                       /* turn on 100 Mbps LED (LED_LINK100) */
+                       ledover |= PHY_M_LED_MO_100(MO_LED_ON);
+               }
+
+               if (ledover)
+                       gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
+
+       }
        /* Enable phy interrupt on auto-negotiation complete (or link up) */
        if (sky2->autoneg == AUTONEG_ENABLE)
                gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
@@ -953,6 +978,12 @@ static int sky2_rx_start(struct sky2_port *sky2)
 
        sky2->rx_put = sky2->rx_next = 0;
        sky2_qset(hw, rxq);
+
+       if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
+               /* MAC Rx RAM Read is controlled by hardware */
+               sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
+       }
+
        sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
 
        rx_set_checksum(sky2);
@@ -1035,9 +1066,10 @@ static int sky2_up(struct net_device *dev)
                    RB_RST_SET);
 
        sky2_qset(hw, txqaddr[port]);
-       if (hw->chip_id == CHIP_ID_YUKON_EC_U)
-               sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
 
+       /* Set almost empty threshold */
+       if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
+               sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
 
        sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
                           TX_RING_SIZE - 1);

diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index fd12c28..d1c71f5 100644 (file)
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -5,14 +5,22 @@
 #define _SKY2_H
 
 /* PCI config registers */
-#define PCI_DEV_REG1   0x40
-#define PCI_DEV_REG2   0x44
-#define PCI_DEV_STATUS  0x7c
-#define PCI_OS_PCI_X    (1<<26)
+enum {
+       PCI_DEV_REG1    = 0x40,
+       PCI_DEV_REG2    = 0x44,
+       PCI_DEV_STATUS  = 0x7c,
+       PCI_DEV_REG3    = 0x80,
+       PCI_DEV_REG4    = 0x84,
+       PCI_DEV_REG5    = 0x88,
+};
 
-#define PEX_LNK_STAT   0xf2
-#define PEX_UNC_ERR_STAT 0x104
-#define PEX_DEV_CTRL   0xe8
+enum {
+       PEX_DEV_CAP     = 0xe4,
+       PEX_DEV_CTRL    = 0xe8,
+       PEX_DEV_STA     = 0xea,
+       PEX_LNK_STAT    = 0xf2,
+       PEX_UNC_ERR_STAT= 0x104,
+};
 
 /* Yukon-2 */
 enum pci_dev_reg_1 {
@@ -37,6 +45,25 @@ enum pci_dev_reg_2 {
        PCI_USEDATA64   = 1<<0,         /* Use 64Bit Data bus ext */
 };
 
+/*     PCI_OUR_REG_4           32 bit  Our Register 4 (Yukon-ECU only) */
+enum pci_dev_reg_4 {
+                                       /* (Link Training & Status State Machine) */
+       P_TIMER_VALUE_MSK       = 0xffL<<16,    /* Bit 23..16:  Timer Value Mask */
+                                       /* (Active State Power Management) */
+       P_FORCE_ASPM_REQUEST    = 1<<15, /* Force ASPM Request (A1 only) */
+       P_ASPM_GPHY_LINK_DOWN   = 1<<14, /* GPHY Link Down (A1 only) */
+       P_ASPM_INT_FIFO_EMPTY   = 1<<13, /* Internal FIFO Empty (A1 only) */
+       P_ASPM_CLKRUN_REQUEST   = 1<<12, /* CLKRUN Request (A1 only) */
+
+       P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
+       P_ASPM_CLKREQ_PAD_CTL   = 1<<3, /* CLKREQ PAD Control (A1 only) */
+       P_ASPM_A1_MODE_SELECT   = 1<<2, /* A1 Mode Select (A1 only) */
+       P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
+       P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
+       P_ASPM_CONTROL_MSK      = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
+                                 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
+};
+
 
 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
                               PCI_STATUS_SIG_SYSTEM_ERROR | \
@@ -507,6 +534,16 @@ enum {
 };
 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
 
+/*     Q_F                             32 bit  Flag Register */
+enum {
+       F_ALM_FULL      = 1<<27, /* Rx FIFO: almost full */
+       F_EMPTY         = 1<<27, /* Tx FIFO: empty flag */
+       F_FIFO_EOF      = 1<<26, /* Tag (EOF Flag) bit in FIFO */
+       F_WM_REACHED    = 1<<25, /* Watermark reached */
+       F_M_RX_RAM_DIS  = 1<<24, /* MAC Rx RAM Read Port disable */
+       F_FIFO_LEVEL    = 0x1fL<<16, /* Bit 23..16:     # of Qwords in FIFO */
+       F_WATER_MARK    = 0x0007ffL, /* Bit 10.. 0:     Watermark */
+};
 
 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
 enum {
@@ -909,10 +946,12 @@ enum {
        PHY_BCOM_ID1_C0 = 0x6044,
        PHY_BCOM_ID1_C5 = 0x6047,
 
-       PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
+       PHY_MARV_ID1_B0 = 0x0C23, /* Yukon      (PHY 88E1011) */
        PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
-       PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
-       PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
+       PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC   (PHY 88E1111) */
+       PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2    (PHY 88E1112) */
+       PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE   (PHY 88E3082 Rev.A1) */
+       PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU  (PHY 88E1149 Rev.B2?) */
 };
 
 /* Advertisement register bits */