spi: fsl-dspi: Add ~50ns delay between cs and sck
authorAaron Brice <aaron.brice@datasoft.com>
Fri, 3 Apr 2015 20:39:31 +0000 (13:39 -0700)
committerMark Brown <broonie@kernel.org>
Mon, 6 Apr 2015 17:12:25 +0000 (18:12 +0100)
Add delay between chip select and clock signals, before clock starts and
after clock stops.

Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

No differences found