arm: dart6ul: enable DM_ETH for the dart6ul

This patch converts the dart6ul ethernet support to DM_ETH and cleans
up the legacy ethernet code. The clean up, more specifically:

* moves the fec2 node and pin definition to the carrier board DTS
  since the phy associated with it is on the carrier board and not on
  the SoM;
* add the reset pin associated to each phy;
* separate the ethernet, mdio and reset pins of each fec so that they
  are easier to reference;
* add clock properties to the phy nodes since they are connected to the
  50Mhz ENET[12]_TX_CLK clock of the SoC;
* remove CONFIG_BOARD_EARLY_INIT_F since the function is now empty.

Signed-off-by: Marc Ferland <ferlandm@amotus.ca>

diff --git a/arch/arm/dts/imx6ull-dart-6ul.dts b/arch/arm/dts/imx6ull-dart-6ul.dts
index 4cab1a0..9e217ba 100644 (file)
--- a/arch/arm/dts/imx6ull-dart-6ul.dts
+++ b/arch/arm/dts/imx6ull-dart-6ul.dts
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ * Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
  */
 
 /dts-v1/;
@@ -13,6 +14,28 @@
        compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
 };
 
+&mdio1 {
+       /* KSZ8081RNB (carrier-board) */
+       ethphy1: ethernet-phy@3 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+               clock-names = "rmii-ref";
+               micrel,led-mode = <1>;
+               max-speed = <100>;
+               reg = <3>;
+       };
+};
+
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_rst>;
+       phy-mode = "rmii";
+       phy-handle = <&ethphy1>;
+       phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <100>;
+       status = "okay";
+};
+
 &usdhc2 {
        status = "okay";
 };
@@ -36,4 +59,29 @@
                >;
        };
 
+       pinctrl_enet2: enet2grp {
+               fsl,pins = <
+                       MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
+                       MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
+                       MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+                       MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+                       MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
+                       MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+                       MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+                       MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
+               >;
+       };
+
+       pinctrl_enet2_mdio: mdio_enet2_grp {
+               fsl,pins = <
+                       MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
+                       MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
+               >;
+       };
+
+       pinctrl_enet2_rst: enet2-rst-grp {
+               fsl,pins = <
+                       MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x1b0b0
+               >;
+       };
 };

diff --git a/arch/arm/dts/imx6ull-dart-6ul.dtsi b/arch/arm/dts/imx6ull-dart-6ul.dtsi
index 805a382..fab926f 100644 (file)
--- a/arch/arm/dts/imx6ull-dart-6ul.dtsi
+++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ * Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
  */
 
 / {
@@ -22,36 +23,25 @@
 
 &fec1 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet1>;
+       pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_rst &pinctrl_enet1_mdio>;
        phy-mode = "rmii";
        phy-handle = <&ethphy0>;
+       phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <100>;
        status = "okay";
 
-       mdio1: mdio1 {
+       mdio1: mdio {
                #address-cells = <1>;
                #size-cells = <0>;
 
+               /* KSZ8081RNB (SoM) */
                ethphy0: ethernet-phy@1 {
-                       reg = <1>;
-                       micrel,led-mode = <1>;
-               };
-       };
-};
-
-&fec2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet2>;
-       phy-mode = "rmii";
-       phy-handle = <&ethphy1>;
-       status = "okay";
-
-       mdio2: mdio2 {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               ethphy1: ethernet-phy@2 {
-                       reg = <2>;
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       clocks = <&clks IMX6UL_CLK_ENET_REF>;
+                       clock-names = "rmii-ref";
                        micrel,led-mode = <1>;
+                       max-speed = <100>;
+                       reg = <1>;
                };
        };
 };
@@ -149,10 +139,9 @@
 &iomuxc {
        pinctrl-names = "default";
 
+
        pinctrl_enet1: enet1grp {
                fsl,pins = <
-                       MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
-                       MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0X1b0b0
                        MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
                        MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
                        MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
@@ -164,18 +153,10 @@
                >;
        };
 
-       pinctrl_enet2: enet2grp {
+       pinctrl_enet1_mdio: enet1-mdio-grp {
                fsl,pins = <
-                       MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
-                       MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0X1b0b0
-                       MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
-                       MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
-                       MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
-                       MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
-                       MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
-                       MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
-                       MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
-                       MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
+                       MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
+                       MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
                >;
        };
 
@@ -272,3 +253,11 @@
                >;
        };
 };
+
+&iomuxc_snvs {
+       pinctrl_enet1_rst: enet1-rst-grp {
+               fsl,pins = <
+                       MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00     0x1b0b0
+               >;
+       };
+};

diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c
index 360be75..d997d81 100644 (file)
--- a/board/variscite/dart_6ul/dart_6ul.c
+++ b/board/variscite/dart_6ul/dart_6ul.c
@@ -2,6 +2,7 @@
 /*
  * Copyright (C) 2015-2019 Variscite Ltd.
  * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ * Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
  */
 
 #include <init.h>
@@ -18,9 +19,6 @@
 #include <linux/bitops.h>
 #include <malloc.h>
 #include <miiphy.h>
-#include <netdev.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -97,67 +95,6 @@ static void setup_gpmi_nand(void)
 #endif
 
 #ifdef CONFIG_FEC_MXC
-#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
-#define ENET_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE       | \
-                          PAD_CTL_SPEED_HIGH  | PAD_CTL_DSE_48ohm | \
-                          PAD_CTL_SRE_FAST)
-#define MDIO_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE      | \
-                          PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | \
-                          PAD_CTL_ODE)
-/*
- * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
- * be used for ENET1 or ENET2, cannot be used for both.
- */
-static iomux_v3_cfg_t const fec1_pads[] = {
-       MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
-       MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
-       MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const fec2_pads[] = {
-       MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
-       MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
-       MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_fec(int fec_id)
-{
-       if (fec_id == 0)
-               imx_iomux_v3_setup_multiple_pads(fec1_pads,
-                                                ARRAY_SIZE(fec1_pads));
-       else
-               imx_iomux_v3_setup_multiple_pads(fec2_pads,
-                                                ARRAY_SIZE(fec2_pads));
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-       int ret = 0;
-
-       ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
-                                     CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
-
-#if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
-       /* USB Ethernet Gadget */
-       usb_eth_initialize(bis);
-#endif
-       return ret;
-}
-
 static int setup_fec(int fec_id)
 {
        struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -203,13 +140,6 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif /* CONFIG_FEC_MXC */
 
-int board_early_init_f(void)
-{
-       setup_iomux_fec(CONFIG_FEC_ENET_DEV);
-
-       return 0;
-}
-
 int board_init(void)
 {
        /* Address of boot parameters */

diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c
index 071f049..91d470f 100644 (file)
--- a/board/variscite/dart_6ul/spl.c
+++ b/board/variscite/dart_6ul/spl.c
@@ -199,9 +199,6 @@ void board_init_f(ulong dummy)
 
        setup_iomux_uart();
 
-       /* iomux and setup of i2c */
-       board_early_init_f();
-
        /* UART clocks enabled and gd valid - init serial console */
        preloader_console_init();
 

diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index 7218825..b1afcf1 100644 (file)
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -18,7 +18,6 @@ CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
 CONFIG_BOOTDELAY=3
 # CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_USB_HOST_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_DM=y
@@ -42,6 +41,7 @@ CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y

diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h
index 4eb50f8..dccfa03 100644 (file)
--- a/include/configs/dart_6ul.h
+++ b/include/configs/dart_6ul.h
@@ -22,16 +22,9 @@
 
 #ifdef CONFIG_CMD_NET
 #define CONFIG_FEC_ENET_DEV            0
-
 #if (CONFIG_FEC_ENET_DEV == 0)
-#define IMX_FEC_BASE                   ENET_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR         0x1
-#define CONFIG_FEC_XCV_TYPE            RMII
 #define CONFIG_ETHPRIME                        "eth0"
 #elif (CONFIG_FEC_ENET_DEV == 1)
-#define IMX_FEC_BASE                   ENET2_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR         0x3
-#define CONFIG_FEC_XCV_TYPE            RMII
 #define CONFIG_ETHPRIME                        "eth1"
 #endif
 #endif