Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 3533/1: Implement the __raw_(read|write)_can_lock functions on ARM
  [ARM] 3530/1: PXA Mainstone: prevent double enable_irq() in pcmcia
  [ARM] 3529/1: s3c24xx: fix restoring control register with undefined instruction

diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 98356f8..02e188d 100644 (file)
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -95,7 +95,10 @@ static void __init mainstone_init_irq(void)
        for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
                set_irq_chip(irq, &mainstone_irq_chip);
                set_irq_handler(irq, do_level_IRQ);
-               set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+               if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
+                       set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
+               else
+                       set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
        set_irq_flags(MAINSTONE_IRQ(8), 0);
        set_irq_flags(MAINSTONE_IRQ(12), 0);

diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index 832fb86..73de2ea 100644 (file)
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -59,8 +59,7 @@ ENTRY(s3c2410_cpu_suspend)
        mrc     p15, 0, r5, c13, c0, 0  @ PID
        mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
        mrc     p15, 0, r7, c2, c0, 0   @ translation table base address
-       mrc     p15, 0, r8, c2, c0, 0   @ auxiliary control register
-       mrc     p15, 0, r9, c1, c0, 0   @ control register
+       mrc     p15, 0, r8, c1, c0, 0   @ control register
 
        stmia   r0, { r4 - r13 }
 
@@ -165,7 +164,6 @@ ENTRY(s3c2410_cpu_resume)
        mcr     p15, 0, r5, c13, c0, 0          @ PID
        mcr     p15, 0, r6, c3, c0, 0           @ Domain ID
        mcr     p15, 0, r7, c2, c0, 0           @ translation table base
-       mcr     p15, 0, r8, c1, c1, 0           @ auxilliary control
 
 #ifdef CONFIG_DEBUG_RESUME
        mov     r3, #'R'
@@ -173,7 +171,7 @@ ENTRY(s3c2410_cpu_resume)
 #endif
 
        ldr     r2, =resume_with_mmu
-       mcr     p15, 0, r9, c1, c0, 0           @ turn on MMU, etc
+       mcr     p15, 0, r8, c1, c0, 0           @ turn on MMU, etc
        nop                                     @ second-to-last before mmu
        mov     pc, r2                          @ go back to virtual address
 

diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h
index 43ad4e5..406ca97 100644 (file)
--- a/include/asm-arm/spinlock.h
+++ b/include/asm-arm/spinlock.h
@@ -142,6 +142,9 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
        : "cc");
 }
 
+/* write_can_lock - would write_trylock() succeed? */
+#define __raw_write_can_lock(x)                ((x)->lock == 0x80000000)
+
 /*
  * Read locks are a bit more hairy:
  *  - Exclusively load the lock value.
@@ -198,4 +201,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
 
 #define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
 
+/* read_can_lock - would read_trylock() succeed? */
+#define __raw_read_can_lock(x)         ((x)->lock < 0x80000000)
+
 #endif /* __ASM_SPINLOCK_H */