imx-drm: match ipu_di_signal_cfg's clk_pol with its description.

According to the datasheet, setting the di0_polarity_disp_clk
field in the GENERAL di register sets the output clock polarity
to active high.

Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --cc drivers/staging/imx-drm/ipu-v3/ipu-di.c
Simple merge

diff --cc drivers/staging/imx-drm/ipuv3-crtc.c
Simple merge