drm/nve0/fifo: mask unhandled intr bits when seen, rather than all intrs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index dbc3ff6..6853cd2 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -743,9 +743,9 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
        }
 
        if (stat) {
-               nv_fatal(priv, "unhandled status 0x%08x\n", stat);
+               nv_error(priv, "INTR 0x%08x\n", stat);
+               nv_mask(priv, 0x002140, stat, 0x00000000);
                nv_wr32(priv, 0x002100, stat);
-               nv_wr32(priv, 0x002140, 0);
        }
 }