dpll_param_p = &core_dpll_param_l3_190[clk_index];
else if(omap_revision() == OMAP4430_ES2_0)
dpll_param_p = &core_dpll_param[clk_index];
- else if(omap_revision() == OMAP4430_ES2_1)
+ else if(omap_revision() >= OMAP4430_ES2_1)
dpll_param_p = &core_dpll_param_ddr400[clk_index];
/* Disable autoidle */
dpll_param_p = &core_dpll_param_l3_190[clk_index];
else if(omap_revision() == OMAP4430_ES2_0)
dpll_param_p = &core_dpll_param[clk_index];
- else if(omap_revision() == OMAP4430_ES2_1)
+ else if(omap_revision() >= OMAP4430_ES2_1)
dpll_param_p = &core_dpll_param_ddr400[clk_index];
/* Disable autoidle */
dpll_param_p = &core_dpll_param_l3_190[6];
else if(omap_revision() == OMAP4430_ES2_0)
dpll_param_p = &core_dpll_param[6];
- else if(omap_revision() == OMAP4430_ES2_1)
+ else if(omap_revision() >= OMAP4430_ES2_1)
dpll_param_p = &core_dpll_param_ddr400[6];
/* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
ddr_regs = &ddr_regs_380_mhz;
else if (rev == OMAP4430_ES2_0)
ddr_regs = &ddr_regs_200_mhz_2cs;
- else if (rev == OMAP4430_ES2_1)
+ else if (rev >= OMAP4430_ES2_1)
ddr_regs = &ddr_regs_400_mhz_2cs;
/*
* set SDRAM CONFIG register
*(volatile int*)(0x4A307BA0) = 0x316112;
else if (rev == OMAP4430_ES2_0)
*(volatile int*)(0x4A307BA0) = 0x296112;
- else if (rev == OMAP4430_ES2_1)
+ else if (rev >= OMAP4430_ES2_1)
*(volatile int*)(0x4A307BA0) = 0x2A6112;
*(volatile int*)(0x4A307BA0) |= 0x1000000;
while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
unsigned int omap_revision(void)
{
+ unsigned int chip_rev = 0;
unsigned int rev = cortex_a9_rev();
switch(rev) {
case 0x410FC091:
return OMAP4430_ES1_0;
case 0x411FC092:
- if (__raw_readl(0x4a002204) == 0x3b95c02f)
+ chip_rev = (__raw_readl(OMAP44XX_CTRL_ID_CODE) >> 28) & 0xF;
+ if (chip_rev == 3)
return OMAP4430_ES2_1;
+ else if (chip_rev >= 4)
+ return OMAP4430_ES2_2;
else
return OMAP4430_ES2_0;
- default:
- return OMAP4430_SILICON_ID_INVALID;
}
+ return OMAP4430_SILICON_ID_INVALID;
}
#define OMAP4430_ES1_0 1
#define OMAP4430_ES2_0 2
#define OMAP4430_ES2_1 3
+#define OMAP4430_ES2_2 4
#ifndef __ASSEMBLY__
/*Functions for silicon revision */
#define OMAP44XX_L4_IO_BASE OMAP44XX_CORE_L4_IO_BASE
/* CONTROL */
-//#define OMAP44XX_CTRL_BASE (OMAP44XX_L4_IO_BASE+0x2000)
+#define OMAP44XX_CTRL_GEN_CORE_BASE (OMAP44XX_L4_IO_BASE+0x2000)
+#define OMAP44XX_CTRL_ID_CODE (OMAP44XX_CTRL_GEN_CORE_BASE + 0x204)
+
#define OMAP44XX_CTRL_BASE 0x4a100000
/* TAP information dont know for 3430*/