dmaengine: shdma: add chcr_ie_bit
authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Fri, 17 Jun 2011 08:20:51 +0000 (08:20 +0000)
committerPaul Mundt <lethal@linux-sh.org>
Tue, 21 Jun 2011 08:56:01 +0000 (17:56 +0900)
IE bit position on CHCR register is not same in all DMAC.
This patch adds new "chcr_ie_bit" to decide it.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
drivers/dma/shdma.c
drivers/dma/shdma.h
include/linux/sh_dma.h

index 40900c1..9412de3 100644 (file)
@@ -181,17 +181,19 @@ static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
 
 static void dmae_start(struct sh_dmae_chan *sh_chan)
 {
+       struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
        u32 chcr = chcr_read(sh_chan);
 
-       chcr |= CHCR_DE | CHCR_IE;
+       chcr |= CHCR_DE | shdev->chcr_ie_bit;
        chcr_write(sh_chan, chcr & ~CHCR_TE);
 }
 
 static void dmae_halt(struct sh_dmae_chan *sh_chan)
 {
+       struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
        u32 chcr = chcr_read(sh_chan);
 
-       chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
+       chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
        chcr_write(sh_chan, chcr);
 }
 
@@ -1157,6 +1159,11 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
        else
                shdev->chcr_offset = CHCR;
 
+       if (pdata->chcr_ie_bit)
+               shdev->chcr_ie_bit = pdata->chcr_ie_bit;
+       else
+               shdev->chcr_ie_bit = CHCR_IE;
+
        platform_set_drvdata(pdev, shdev);
 
        pm_runtime_enable(&pdev->dev);
index 6f064ca..dc56576 100644 (file)
@@ -48,6 +48,7 @@ struct sh_dmae_device {
        u32 __iomem *chan_reg;
        u16 __iomem *dmars;
        unsigned int chcr_offset;
+       u32 chcr_ie_bit;
 };
 
 #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)
index 41fe4c2..96803aa 100644 (file)
@@ -63,6 +63,7 @@ struct sh_dmae_pdata {
        int ts_shift_num;
        u16 dmaor_init;
        unsigned int chcr_offset;
+       u32 chcr_ie_bit;
 };
 
 /* DMA register */