net: fec_mxc: support i.MX8M with CLK_CCF
authorPeng Fan <peng.fan@nxp.com>
Fri, 25 Oct 2019 09:48:02 +0000 (09:48 +0000)
committerStefano Babic <sbabic@denx.de>
Tue, 5 Nov 2019 09:27:18 +0000 (10:27 +0100)
Add more clks for fec_mxc according to Linux Kernel 5.4.0-rc1
drivers/net/ethernet/freescale/fec_main.c.

Since i.MX8MQ not support CLK_CCF, so add a check to restrict
the code only effect when CONFIG_IMX8M and CONFIG_CLK_CCF both defined.

Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
drivers/net/fec_mxc.c
drivers/net/fec_mxc.h

index 080dbcf..131d199 100644 (file)
@@ -123,30 +123,38 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
        return val;
 }
 
+#ifndef imx_get_fecclk
+u32 __weak imx_get_fecclk(void)
+{
+       return 0;
+}
+#endif
+
 static int fec_get_clk_rate(void *udev, int idx)
 {
-#if IS_ENABLED(CONFIG_IMX8)
        struct fec_priv *fec;
        struct udevice *dev;
        int ret;
 
-       dev = udev;
-       if (!dev) {
-               ret = uclass_get_device(UCLASS_ETH, idx, &dev);
-               if (ret < 0) {
-                       debug("Can't get FEC udev: %d\n", ret);
-                       return ret;
+       if (IS_ENABLED(CONFIG_IMX8) ||
+           CONFIG_IS_ENABLED(CLK_CCF)) {
+               dev = udev;
+               if (!dev) {
+                       ret = uclass_get_device(UCLASS_ETH, idx, &dev);
+                       if (ret < 0) {
+                               debug("Can't get FEC udev: %d\n", ret);
+                               return ret;
+                       }
                }
-       }
 
-       fec = dev_get_priv(dev);
-       if (fec)
-               return fec->clk_rate;
+               fec = dev_get_priv(dev);
+               if (fec)
+                       return fec->clk_rate;
 
-       return -EINVAL;
-#else
-       return imx_get_fecclk();
-#endif
+               return -EINVAL;
+       } else {
+               return imx_get_fecclk();
+       }
 }
 
 static void fec_mii_setspeed(struct ethernet_regs *eth)
@@ -1335,6 +1343,47 @@ static int fecmxc_probe(struct udevice *dev)
                        return ret;
                }
 
+               priv->clk_rate = clk_get_rate(&priv->ipg_clk);
+       } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
+               ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
+               if (ret < 0) {
+                       debug("Can't get FEC ipg clk: %d\n", ret);
+                       return ret;
+               }
+               ret = clk_enable(&priv->ipg_clk);
+               if(ret)
+                       return ret;
+
+               ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
+               if (ret < 0) {
+                       debug("Can't get FEC ahb clk: %d\n", ret);
+                       return ret;
+               }
+               ret = clk_enable(&priv->ahb_clk);
+               if (ret)
+                       return ret;
+
+               ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
+               if (!ret) {
+                       ret = clk_enable(&priv->clk_enet_out);
+                       if (ret)
+                               return ret;
+               }
+
+               ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
+               if (!ret) {
+                       ret = clk_enable(&priv->clk_ref);
+                       if (ret)
+                               return ret;
+               }
+
+               ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
+               if (!ret) {
+                       ret = clk_enable(&priv->clk_ptp);
+                       if (ret)
+                               return ret;
+               }
+
                priv->clk_rate = clk_get_rate(&priv->ipg_clk);
        }
 
index e5f2dd7..723b06a 100644 (file)
@@ -264,6 +264,10 @@ struct fec_priv {
        u32 interface;
 #endif
        struct clk ipg_clk;
+       struct clk ahb_clk;
+       struct clk clk_enet_out;
+       struct clk clk_ref;
+       struct clk clk_ptp;
        u32 clk_rate;
 };