configs: socfpga: Add CRC32 support
authorNaresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Tue, 19 Aug 2025 04:24:04 +0000 (21:24 -0700)
committerTien Fong Chee <tien.fong.chee@intel.com>
Tue, 30 Sep 2025 06:29:52 +0000 (14:29 +0800)
CRC32 support for SoC64 devices is added.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
configs/socfpga_agilex_defconfig
configs/socfpga_n5x_defconfig
configs/socfpga_stratix10_defconfig

index 1c3664b..44c12db 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
+CONFIG_SPL_CRC32=y
 CONFIG_SPL_CACHE=y
 CONFIG_SPL_MTD=y
 CONFIG_SPL_SPI_FLASH_MTD=y
index 8795566..d501fcd 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
 CONFIG_SPL_CACHE=y
+CONFIG_SPL_CRC32=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
 CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex"
index 90134d8..fe191d0 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
+CONFIG_SPL_CRC32=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000
 CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex"