drivers: ddr: altera: Correct DDR calibration status check
authorNaresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Fri, 8 Aug 2025 09:42:42 +0000 (02:42 -0700)
committerTien Fong Chee <tien.fong.chee@intel.com>
Tue, 30 Sep 2025 06:29:53 +0000 (14:29 +0800)
Bit 3 of the seq2core register is no longer set to indicate
calibration completion. Instead, added polling of the seq2core
register until it reads 0b00000111, signaling that the Nios
processor has started the calibration process.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
drivers/ddr/altera/sdram_soc64.c
drivers/ddr/altera/sdram_soc64.h

index f8fc920..2d0093c 100644 (file)
@@ -85,11 +85,11 @@ int emif_reset(struct altera_sdram_plat *plat)
        debug("DDR: Triggerring emif reset\n");
        hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
 
-       /* if seq2core[3] = 0, we are good */
+       /* if seq2core[2:0] = 0b0000_0111, we are good */
        ret = wait_for_bit_le32((const void *)(plat->hmc +
                                 RSTHANDSHAKESTAT),
-                                DDR_HMC_SEQ2CORE_INT_RESP_MASK,
-                                false, 1000, false);
+                                DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK,
+                                true, 1000, false);
        if (ret) {
                printf("DDR: failed to get ack from EMIF\n");
                return ret;
index 6031cef..6fe0653 100644 (file)
@@ -77,7 +77,7 @@ struct altera_sdram_plat {
 #define DDR_HMC_INTMODE_INTMODE_SET_MSK                BIT(0)
 #define DDR_HMC_RSTHANDSHAKE_MASK              0x0000000f
 #define DDR_HMC_CORE2SEQ_INT_REQ               0x0000000f
-#define DDR_HMC_SEQ2CORE_INT_RESP_MASK         BIT(3)
+#define DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK      GENMASK(2, 0)
 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK                0x001f1f1f
 
 #define        DDR_HMC_ERRINTEN_INTMASK                                \