[PATCH] powerpc: Fix use of LOADBASE in merge tree

The merge-tree version of LOADBASE actually loads the whole given
address from the toc for ppc64.  The matching OFF macro adjust for
this, using an offset of 0 for ppc64, but we weren't using that in
power4_idle.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

diff --git a/arch/powerpc/kernel/idle_power4.S b/arch/powerpc/kernel/idle_power4.S
index 5596fad..1494e2f 100644 (file)
--- a/arch/powerpc/kernel/idle_power4.S
+++ b/arch/powerpc/kernel/idle_power4.S
@@ -39,13 +39,13 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
         * can be cleared by CPU init after the fixups are done
         */
        LOADBASE(r3,cur_cpu_spec)
-       ld      r4,cur_cpu_spec@l(r3)
+       ld      r4,OFF(cur_cpu_spec)(r3)
        ld      r4,CPU_SPEC_FEATURES(r4)
        andi.   r0,r4,CPU_FTR_CAN_NAP
        beqlr
        /* Now check if user or arch enabled NAP mode */
        LOADBASE(r3,powersave_nap)
-       lwz     r4,powersave_nap@l(r3)
+       lwz     r4,OFF(powersave_nap)(r3)
        cmpwi   0,r4,0
        beqlr