ARM: dts: imx27 phyCARD-S pinctrl

Add pinctrl nodes and properties for phyCARD-S device nodes.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
index 9e2fe99988a6aa8062cc5a204fde7811bd2fc2b0..c37c74a12e05ca78d7a735e1af3f6a0a29fc0f44 100644 (file)
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -57,6 +57,8 @@
 };
 
 &i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
        status = "okay";
 
        rtc@51 {
@@ -71,7 +73,53 @@
        };
 };
 
+&iomuxc {
+       imx27-phycard-s-rdk {
+               pinctrl_i2c1: i2c1grp {
+                       fsl,pins = <
+                               MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+                               MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+                       >;
+               };
+
+               pinctrl_owire1: owire1grp {
+                       fsl,pins = <
+                               MX27_PAD_RTCK__OWIRE 0x0
+                       >;
+               };
+
+               pinctrl_uart1: uart1grp {
+                       fsl,pins = <
+                               MX27_PAD_UART1_TXD__UART1_TXD 0x0
+                               MX27_PAD_UART1_RXD__UART1_RXD 0x0
+                               MX27_PAD_UART1_CTS__UART1_CTS 0x0
+                               MX27_PAD_UART1_RTS__UART1_RTS 0x0
+                       >;
+               };
+
+               pinctrl_uart2: uart2grp {
+                       fsl,pins = <
+                               MX27_PAD_UART2_TXD__UART2_TXD 0x0
+                               MX27_PAD_UART2_RXD__UART2_RXD 0x0
+                               MX27_PAD_UART2_CTS__UART2_CTS 0x0
+                               MX27_PAD_UART2_RTS__UART2_RTS 0x0
+                       >;
+               };
+
+               pinctrl_uart3: uart3grp {
+                       fsl,pins = <
+                               MX27_PAD_UART3_TXD__UART3_TXD 0x0
+                               MX27_PAD_UART3_RXD__UART3_RXD 0x0
+                               MX27_PAD_UART3_CTS__UART3_CTS 0x0
+                               MX27_PAD_UART3_RTS__UART3_RTS 0x0
+                       >;
+               };
+       };
+};
+
 &owire {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_owire1>;
        status = "okay";
 };
 
@@ -82,15 +130,21 @@
 
 &uart1 {
        fsl,uart-has-rtscts;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 
 &uart2 {
        fsl,uart-has-rtscts;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
        status = "okay";
 };
 
 &uart3 {
        fsl,uart-has-rtscts;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart3>;
        status = "okay";
 };

diff --cc arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
Simple merge

diff --cc arch/arm/boot/dts/imx27.dtsi
Simple merge