[NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
[NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
[NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
- [AO_Output_Control_Register] = { 0x1ac, 2 },
+ [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
[AI_Mode_3_Register] = { 0x1ae, 2 },
};
if (cmd->scan_end_arg > 1) {
devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
ni_stc_writew(dev,
- AO_Number_Of_Channels(cmd->scan_end_arg - 1) |
- AO_UPDATE_Output_Select(AO_Update_Output_High_Z),
- AO_Output_Control_Register);
+ NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) |
+ NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ,
+ NISTC_AO_OUT_CTRL_REG);
} else {
unsigned bits;
devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
- bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
+ bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
if (devpriv->is_m_series || devpriv->is_6xxx) {
- bits |= AO_Number_Of_Channels(0);
+ bits |= NISTC_AO_OUT_CTRL_CHANS(0);
} else {
bits |=
- AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
+ NISTC_AO_OUT_CTRL_CHANS(CR_CHAN(cmd->chanlist[0]));
}
- ni_stc_writew(dev, bits, AO_Output_Control_Register);
+ ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
}
ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
NISTC_AO_PERSONAL_UPDATE_PW |
NISTC_AO_PERSONAL_TMRDACWR_PW,
NISTC_AO_PERSONAL_REG);
- ni_stc_writew(dev, 0, AO_Output_Control_Register);
+ ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
devpriv->ao_cmd1 = 0;
ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
#define NISTC_DAC_FIFO_CLR_REG 84
#define NISTC_WR_STROBE3_REG 85
+#define NISTC_AO_OUT_CTRL_REG 86
+#define NISTC_AO_OUT_CTRL_EXT_GATE_ENA BIT(15)
+#define NISTC_AO_OUT_CTRL_EXT_GATE_SEL(x) (((x) & 0x1f) << 10)
+#define NISTC_AO_OUT_CTRL_CHANS(x) (((x) & 0xf) << 6)
+#define NISTC_AO_OUT_CTRL_UPDATE2_SEL(x) (((x) & 0x3) << 4)
+#define NISTC_AO_OUT_CTRL_EXT_GATE_POL BIT(3)
+#define NISTC_AO_OUT_CTRL_UPDATE2_TOGGLE BIT(2)
+#define NISTC_AO_OUT_CTRL_UPDATE_SEL(x) (((x) & 0x3) << 0)
+#define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ NISTC_AO_OUT_CTRL_UPDATE_SEL(0)
+#define NISTC_AO_OUT_CTRL_UPDATE_SEL_GND NISTC_AO_OUT_CTRL_UPDATE_SEL(1)
+#define NISTC_AO_OUT_CTRL_UPDATE_SEL_LOW NISTC_AO_OUT_CTRL_UPDATE_SEL(2)
+#define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGH NISTC_AO_OUT_CTRL_UPDATE_SEL(3)
+
#define AI_Status_1_Register 2
#define Interrupt_A_St 0x8000
#define AI_FIFO_Full_St 0x4000
#define AO_BC_Save_Registers 18
#define AO_UC_Save_Registers 20
-#define AO_Output_Control_Register 86
-#define AO_External_Gate_Enable _bit15
-#define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
-#define AO_Number_Of_Channels(x) (((x)&0xf)<<6)
-#define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
-#define AO_External_Gate_Polarity _bit3
-#define AO_UPDATE2_Output_Toggle _bit2
-enum ao_update_output_selection {
- AO_Update_Output_High_Z = 0,
- AO_Update_Output_Ground = 1,
- AO_Update_Output_Enable_Low = 2,
- AO_Update_Output_Enable_High = 3
-};
-static unsigned AO_UPDATE_Output_Select(enum ao_update_output_selection
- selection)
-{
- return selection & 0x3;
-}
-
#define AI_Mode_3_Register 87
#define AI_Trigger_Length _bit15
#define AI_Delay_START _bit14