diff -uNr linux-2.6.20.vanilla/drivers/video/Kconfig linux-2.6.20/drivers/video/Kconfig
---- linux-2.6.20.vanilla/drivers/video/Kconfig 2007-02-10 19:02:14.000000000 +0100
-+++ linux-2.6.20/drivers/video/Kconfig 2007-02-11 16:39:54.000000000 +0100
-@@ -1147,6 +1147,18 @@
+--- linux-2.6.20.vanilla/drivers/video/Kconfig 2007-03-24 21:25:52.000000000 +0100
++++ linux-2.6.20/drivers/video/Kconfig 2007-03-28 22:53:44.000000000 +0200
+@@ -1147,6 +1147,15 @@
help
If you have a S3 Trio say Y. Say N for S3 Virge.
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ help
-+ This is a MQ200 driver tested only on Simens SIMpads. You may need to
-+ boot your SIMpad with a 2.4 SIMpad Kernel first in order to use this
-+ driver. This is also needed if the SIMpad lost his power
-+ connection (empty accu or accu disconnect).
++ This is a MQ200 driver tested only on Siemens SIMpads.
+
config FB_SAVAGE
tristate "S3 Savage support"
depends on FB && PCI && EXPERIMENTAL
diff -uNr linux-2.6.20.vanilla/drivers/video/Makefile linux-2.6.20/drivers/video/Makefile
---- linux-2.6.20.vanilla/drivers/video/Makefile 2007-02-10 19:02:14.000000000 +0100
-+++ linux-2.6.20/drivers/video/Makefile 2007-02-11 16:40:07.000000000 +0100
+--- linux-2.6.20.vanilla/drivers/video/Makefile 2007-03-24 21:25:52.000000000 +0100
++++ linux-2.6.20/drivers/video/Makefile 2007-03-28 22:53:44.000000000 +0200
@@ -30,6 +30,7 @@
obj-$(CONFIG_FB_PM2) += pm2fb.o
obj-$(CONFIG_FB_PM3) += pm3fb.o
obj-$(CONFIG_FB_MATROX) += matrox/
obj-$(CONFIG_FB_RIVA) += riva/ vgastate.o
obj-$(CONFIG_FB_NVIDIA) += nvidia/
+diff -uNr linux-2.6.20.vanilla/drivers/video/backlight/Kconfig linux-2.6.20/drivers/video/backlight/Kconfig
+--- linux-2.6.20.vanilla/drivers/video/backlight/Kconfig 2007-03-24 21:25:53.000000000 +0100
++++ linux-2.6.20/drivers/video/backlight/Kconfig 2007-03-28 22:53:44.000000000 +0200
+@@ -66,3 +66,10 @@
+ If you have a HP Jornada 680, say y to enable the
+ backlight driver.
+
++config FB_MQ200_LCD
++ bool "MQ200 LCD class implemetation"
++ depends on SA1100_SIMPAD && LCD_DEVICE
++
++config FB_MQ200_BACKLIGHT
++ bool "MQ200 Backlight class implementation"
++ depends on SA1100_SIMPAD && BACKLIGHT_DEVICE
+diff -uNr linux-2.6.20.vanilla/drivers/video/backlight/Makefile linux-2.6.20/drivers/video/backlight/Makefile
+--- linux-2.6.20.vanilla/drivers/video/backlight/Makefile 2007-03-24 21:25:53.000000000 +0100
++++ linux-2.6.20/drivers/video/backlight/Makefile 2007-03-28 22:53:44.000000000 +0200
+@@ -5,3 +5,5 @@
+ obj-$(CONFIG_BACKLIGHT_CORGI) += corgi_bl.o
+ obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o
+ obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
++obj-$(CONFIG_FB_MQ200_BACKLIGHT) += simpad_bl.o
++obj-$(CONFIG_FB_MQ200_LCD) += simpad_lcd.o
+diff -uNr linux-2.6.20.vanilla/drivers/video/backlight/simpad_bl.c linux-2.6.20/drivers/video/backlight/simpad_bl.c
+--- linux-2.6.20.vanilla/drivers/video/backlight/simpad_bl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.20/drivers/video/backlight/simpad_bl.c 2007-03-28 22:53:44.000000000 +0200
+@@ -0,0 +1,109 @@
++/*
++ * GPLv2 <zecke@handhelds.org
++ *
++ * Implementation of the backlight_driver for
++ * the mq200 framebuffer
++ *
++ * 2007/03/17 mrdata:
++ * - small changes simpad_bl_get_brightness()
++ * simpad_bl_set_brightness()
++ * - new function simpad_bl_update_status()
++ * - changed struct backlight_properties simpad_bl_props()
++ * to new one
++ * - changed __init simpad_bl_init() -> backlight_device_register
++ *
++ * 2007/03/24 mrdata
++ * - added .brightness=127 in
++ * struct backlight_properties simpad_bl_props()
++ */
++#include <asm/types.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++
++#include <linux/device.h>
++#include <linux/backlight.h>
++#include <linux/fb.h>
++
++#include "../mq200/mq200_data.h"
++
++#define SIMPAD_BACKLIGHT_MASK 0x00a10044
++#define MAX_BRIGHT 254
++#define REGISTER_BASE 0xf2e00000
++
++
++static int simpad_bl_get_brightness(struct backlight_device *dev)
++{
++ u32 pwmctl;
++
++ pwmctl = readl(FP0FR(REGISTER_BASE));
++ pwmctl &= ~SIMPAD_BACKLIGHT_MASK;
++ pwmctl = pwmctl >> 8;
++ pwmctl = MAX_BRIGHT - pwmctl;
++
++ return pwmctl;
++}
++
++static int simpad_bl_set_brightness(int bright)
++{
++ union fp0fr fp0fr;
++ unsigned long dutyCycle, pwmcontrol;
++
++ if(bright > MAX_BRIGHT)
++ bright = MAX_BRIGHT;
++
++ /*
++ * Determine dutyCycle.
++ * Note: the lower the value, the brighter the display!
++ */
++
++ dutyCycle = MAX_BRIGHT - bright;
++
++ /*
++ *Configure PWM0 (source clock = oscillator clock, pwm always enabled,
++ *zero, clock pre-divider = 4) pwm frequency = 12.0kHz
++ */
++ fp0fr.whole = readl(FP0FR(REGISTER_BASE));
++ pwmcontrol = fp0fr.whole & 0xffff00ff;
++ fp0fr.whole &= 0xffffff00;
++ fp0fr.whole |= 0x00000044;
++ writel(fp0fr.whole, FP0FR(REGISTER_BASE));
++
++ /* Write to pwm duty cycle register. */
++ fp0fr.whole = dutyCycle << 8;
++ fp0fr.whole &= 0x0000ff00;
++ fp0fr.whole |= pwmcontrol;
++ writel(fp0fr.whole, FP0FR(REGISTER_BASE));
++
++ return 0;
++}
++
++static int simpad_bl_update_status(struct backlight_device *dev)
++{
++ return simpad_bl_set_brightness(dev->props->brightness);
++}
++
++static struct backlight_properties simpad_bl_props = {
++ .owner = THIS_MODULE,
++ .update_status = simpad_bl_update_status,
++ .get_brightness = simpad_bl_get_brightness,
++ .brightness=127,
++ .max_brightness = MAX_BRIGHT,
++};
++
++static struct backlight_device *simpad_bl_device = NULL;
++
++static int __init simpad_bl_init(void) {
++ simpad_bl_device = backlight_device_register("mq200_fb0", NULL,
++ NULL, &simpad_bl_props);
++ return simpad_bl_device != NULL;
++}
++
++static void __exit simpad_bl_exit(void) {
++ backlight_device_unregister(simpad_bl_device);
++}
++
++
++module_init(simpad_bl_init);
++module_exit(simpad_bl_exit);
++MODULE_AUTHOR("Holger Hans Peter Freyther");
++MODULE_LICENSE("GPL");
+diff -uNr linux-2.6.20.vanilla/drivers/video/backlight/simpad_lcd.c linux-2.6.20/drivers/video/backlight/simpad_lcd.c
+--- linux-2.6.20.vanilla/drivers/video/backlight/simpad_lcd.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.20/drivers/video/backlight/simpad_lcd.c 2007-03-28 22:58:41.000000000 +0200
+@@ -0,0 +1,80 @@
++/*
++ * GPLv2 <zecke@handhelds.org
++ *
++ * Implementation of the lcd_driver for the mq200 framebuffer
++ *
++ * 2007/03/24 mrdata:
++ * - added simpad_lcd_get_contrast()
++ * - added simpad_lcd_set_contrast()
++ * - modify struct lcd_properties simpad_lcd_props
++ */
++#include <asm/arch/simpad.h>
++#include <asm/hardware.h>
++
++#include <linux/device.h>
++#include <linux/lcd.h>
++
++extern long get_cs3_shadow(void);
++extern void set_cs3_bit(int);
++extern void clear_cs3_bit(int);
++
++#define UNUSED(x) x=x
++
++static int simpad_lcd_get_power(struct lcd_device* dev)
++{
++ UNUSED(dev);
++
++ return (get_cs3_shadow() & DISPLAY_ON) ? 0 : 4;
++}
++
++static int simpad_lcd_set_power(struct lcd_device* dev, int power)
++{
++ UNUSED(dev);
++
++ if( power == 4 )
++ clear_cs3_bit(DISPLAY_ON);
++ else
++ set_cs3_bit(DISPLAY_ON);
++
++ return 0;
++}
++
++static int simpad_lcd_get_contrast(struct lcd_device* dev)
++{
++ UNUSED(dev);
++
++ return 0;
++}
++
++static int simpad_lcd_set_contrast(struct lcd_device* dev, int contrast)
++{
++ UNUSED(dev);
++
++ UNUSED(contrast);
++
++ return 0;
++}
++
++static struct lcd_properties simpad_lcd_props = {
++ .owner = THIS_MODULE,
++ .get_power = simpad_lcd_get_power,
++ .set_power = simpad_lcd_set_power,
++ .get_contrast = simpad_lcd_get_contrast,
++ .set_contrast = simpad_lcd_set_contrast,
++ .max_contrast = 0
++};
++
++static struct lcd_device* simpad_lcd_device = NULL;
++
++static int __init simpad_lcd_init(void) {
++ simpad_lcd_device = lcd_device_register("mq200_fb0", NULL,
++ &simpad_lcd_props);
++ return simpad_lcd_device != NULL;
++}
++
++static void __exit simpad_lcd_exit(void) {
++ lcd_device_unregister(simpad_lcd_device);
++}
++
++module_init(simpad_lcd_init);
++module_exit(simpad_lcd_exit);
diff -uNr linux-2.6.20.vanilla/drivers/video/mq200/Makefile linux-2.6.20/drivers/video/mq200/Makefile
--- linux-2.6.20.vanilla/drivers/video/mq200/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.20/drivers/video/mq200/Makefile 2007-02-11 16:41:44.000000000 +0100
++++ linux-2.6.20/drivers/video/mq200/Makefile 2007-03-28 22:53:44.000000000 +0200
@@ -0,0 +1,6 @@
+# Makefile for mq200 video driver
+# 4 Aug 2003, Holger Hans Peter Freyther
-+# 2 Jan 2007, mr nice
++#
+
+obj-$(CONFIG_FB_MQ200) += mq_skeleton.o mq_external.o
+
diff -uNr linux-2.6.20.vanilla/drivers/video/mq200/mq200_data.h linux-2.6.20/drivers/video/mq200/mq200_data.h
--- linux-2.6.20.vanilla/drivers/video/mq200/mq200_data.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.20/drivers/video/mq200/mq200_data.h 2007-02-11 16:41:09.000000000 +0100
-@@ -0,0 +1,893 @@
++++ linux-2.6.20/drivers/video/mq200/mq200_data.h 2007-03-28 22:53:44.000000000 +0200
+@@ -0,0 +1,1120 @@
+/*
+ * From ucLinux mq200fb.c and mq200fb.h
++ *
++ * 2007/03/11 mrdata:
++ * insert registers for graphics controller 2 module
+ */
+
+#ifndef __MQ200_FB_H__
+ start address */
+#define GC0DR(addr) (addr + GC_OFFSET + 0x34) /* alternate window 1
+ start address */
-+#define GC0ER(addr) (addr + GC_OFFSET + 0x38) /* window 1 stride */
-+#define GC0FR(addr) (addr + GC_OFFSET + 0x3c) /* reserved */
++#define GC0ER(addr) (addr + GC_OFFSET + 0x38) /* alternate window 1
++ stride */
++#define GC0FR(addr) (addr + GC_OFFSET + 0x3c) /* alternate window 1
++ line size */
+#define GC10R(addr) (addr + GC_OFFSET + 0x40) /* hardware cursor 1
+ position */
+#define GC11R(addr) (addr + GC_OFFSET + 0x44) /* hardware cursor 1
+ foreground color */
+#define GC13R(addr) (addr + GC_OFFSET + 0x4c) /* hardware cursor 1
+ background color */
++
++/* graphics controller 2 module */
++#define GC20R(addr) (addr + GC_OFFSET + 0x80) /* graphics controller 2
++ control */
++#define GC21R(addr) (addr + GC_OFFSET + 0x84) /* graphics controller
++ CRC control */
++#define GC22R(addr) (addr + GC_OFFSET + 0x88) /* horizontal display 2
++ control */
++#define GC23R(addr) (addr + GC_OFFSET + 0x8c) /* vertical display 2
++ control */
++#define GC24R(addr) (addr + GC_OFFSET + 0x90) /* horizontal sync 2
++ control */
++#define GC25R(addr) (addr + GC_OFFSET + 0x94) /* vertical sync 2
++ control */
++#define GC27R(addr) (addr + GC_OFFSET + 0x9c) /* vertical display 2
++ count */
++#define GC28R(addr) (addr + GC_OFFSET + 0xa0) /* horizontal window 2
++ control */
++#define GC29R(addr) (addr + GC_OFFSET + 0xa4) /* vertical window 2
++ control */
++#define GC2AR(addr) (addr + GC_OFFSET + 0xa8) /* alternate horizontal
++ window 2 control */
++#define GC2BR(addr) (addr + GC_OFFSET + 0xac) /* alternate vertical
++ window 2 control */
++#define GC2CR(addr) (addr + GC_OFFSET + 0xb0) /* window 2
++ start address */
++#define GC2DR(addr) (addr + GC_OFFSET + 0xb4) /* alternate window 2
++ start address */
++#define GC2ER(addr) (addr + GC_OFFSET + 0xb8) /* alternate window 2
++ stride */
++#define GC2FR(addr) (addr + GC_OFFSET + 0xbc) /* alternate window 2
++ line size */
++#define GC30R(addr) (addr + GC_OFFSET + 0xc0) /* hardware cursor 2
++ position */
++#define GC31R(addr) (addr + GC_OFFSET + 0xc4) /* hardware cursor 2
++ start address and
++ offset */
++#define GC32R(addr) (addr + GC_OFFSET + 0xc8) /* hardware cursor 2
++ foreground color */
++#define GC33R(addr) (addr + GC_OFFSET + 0xcc) /* hardware cursor 2
++ background color */
++
+/* graphics engine */
+#define ROP_SRCCOPY 0xCC /* dest = source */
+#define ROP_SRCPAINT 0xEE /* dest = source OR dest */
+ u32 whole;
+};
+
++
++/* graphics controller 2 register */
++union gc20r {
++ struct {
++ u32 ctl_enbl :1; /* Controller 2 Enable */
++ u32 hc_reset :1; /* Horizontal Counter 2 Reset */
++ u32 vc_reset :1; /* Vertical Counter 2 Reset */
++ u32 iwin_enbl :1; /* Image Window 2 Enable */
++ u32 gcd :4; /* Graphics Color Depth (GCD) */
++
++ u32 hc_enbl :1; /* Hardware Cursor 2 Enable */
++ u32 reserved_1 :2;
++ u32 aiwin_enbl :1; /* Alternate Image Window Enable */
++ u32 agcd :4; /* Alternate Graphics Color Depth (AGCD) */
++
++ u32 g2rclk_src :2; /* G2RCLK Source */
++ u32 tm0 :1; /* Test Mode 0 */
++ u32 tm1 :1; /* Test Mode 1 */
++ u32 fd :3; /* G2MCLK First Clock Divisor (FD1) */
++ u32 reserved_2 :1;
++
++ u32 sd :8; /* G2MCLK Second Clock Divisor (SD1) */
++ } part;
++ u32 whole;
++};
++
++/* graphics controller CRC control */
++union gc21r {
++ struct {
++ u32 crc_enbl :1; /* CRC enable */
++ u32 vsync_wait :1; /* CRC input data control waitime of VSYNC */
++ u32 crc_o_sel :2; /* CRC output select */
++ u32 reserved_1 :4;
++ u32 crc_result :22; /* CRC result (read only) */
++ u32 reserved_2 :2;
++ } part;
++ u32 whole;
++};
++
++/* horizontal display 2 control */
++union gc22r {
++ struct {
++ u32 hd2t :12; /* horizontal display 2 total */
++ u32 reserved_1 :4;
++
++ u32 hd2e :12; /* horizontal display 2 end */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* vertical display 2 control */
++union gc23r {
++ struct {
++ u32 vd2t :12; /* vertical display 2 total */
++ u32 reserved_1 :4;
++
++ u32 vd2e :12; /* vertical display 2 end */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* horizontal sync 2 control */
++union gc24r {
++ struct {
++ u32 hs2s :12; /* horizontal sync 2 start */
++ u32 reserved_1 :4;
++
++ u32 hs2e :12; /* horizontal sync 2 end */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* vertical sync 2 control */
++union gc25r {
++ struct {
++ u32 vs2s :12; /* vertical sync 2 start */
++ u32 reserved_1 :4;
++
++ u32 vs2e :12; /* vertical sync 2 end */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* vertical display 2 count */
++union gc27r {
++ struct {
++ u32 vd_cnt :12; /* vertical display 2 count */
++ u32 reverved_1 :20;
++ } part;
++ u32 whole;
++};
++
++/* horizontal window 2 control */
++union gc28r {
++ struct {
++ u32 hw2s :12; /* horizontal window 2 start (HW2S) */
++ u32 reserved_1 :4;
++
++ u32 hw2w :12; /* horizontal window 2 width (HW2W) */
++ u32 w2ald :4; /* window 2 additional line data */
++ } part;
++ u32 whole;
++};
++
++/* vertical window 2 control */
++union gc29r {
++ struct {
++ u32 vw2s :12; /* vertical window 2 start */
++ u32 reserved_1 :4;
++ u32 vw2h :12; /* vertical window 2 height */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* window 2 start address */
++union gc2cr {
++ struct {
++ u32 w2sa :21; /* window 2 start address */
++ u32 reserved_1 :11;
++ } part;
++ u32 whole;
++};
++
++/* window 2 stride */
++union gc2er {
++ struct {
++ s16 w2st; /* window 2 stride */
++ s16 aw2st; /* alternate window 2 stride */
++ } part;
++ u32 whole;
++};
++
++/* hardware cursor 2 position */
++union gc30r {
++ struct {
++ u32 hc2s :12; /* horizontal cursor 2 start */
++ u32 reserved_1 :4;
++ u32 vc2s :12; /* vertical cursor 2 start */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* hardware cursor 2 start address and offset */
++union gc31r {
++ struct {
++ u32 hc2sa :11; /* hardware cursor 2 start address */
++ u32 reserved_1 :5;
++ u32 hc2o :6; /* horizontal cursor 2 offset */
++ u32 reserved_2 :2;
++ u32 vc2o :6; /* vertical cursor 2 offset */
++ u32 reserved_3 :2;
++ } part;
++ u32 whole;
++};
++
++/* hardware cursor 2 foreground color */
++union gc32r {
++ struct {
++ u32 hc2fc :24; /* hardware cursor 2 foreground color */
++ u32 reserved_1 :8;
++ } part;
++ u32 whole;
++};
++
++/* hardware cursor 2 background color */
++union gc33r {
++ struct {
++ u32 hc2bc :24; /* hardware cursor 2 background color */
++ u32 reserved_1 :8;
++ } part;
++ u32 whole;
++};
++
++
+/* primary drawing command register */
+union ge00r {
+ struct {
+#endif
diff -uNr linux-2.6.20.vanilla/drivers/video/mq200/mq_external.c linux-2.6.20/drivers/video/mq200/mq_external.c
--- linux-2.6.20.vanilla/drivers/video/mq200/mq_external.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.20/drivers/video/mq200/mq_external.c 2007-02-11 16:41:09.000000000 +0100
-@@ -0,0 +1,427 @@
++++ linux-2.6.20/drivers/video/mq200/mq_external.c 2007-03-28 22:53:44.000000000 +0200
+@@ -0,0 +1,513 @@
+/*
+ * Copyright (C) 2005 Holger Hans Peter Freyther
+ *
+ * linux/drivers/video/mq200fb.c -- MQ-200 for a frame buffer device
+ * based on linux/driver/video/pm2fb.c
+ *
++ * 2007/03/11 mrdata:
++ * bug found in gc1_reset(), renaming to gc1_gc2_reset()
++ * extend mq200_external_ondisplay() -> LCD for GC2 and CRT for GC1
++ *
+ * Copyright (C) 2000 Lineo, Japan
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+
++#include <asm/hardware.h>
++
+#include "mq200_data.h"
+
+
+{
+ int i;
+ writel(state, PMCSR(register_base));
++ mdelay(300);
+ for (i = 1; ; i++) {
+ udelay(100);
+ if ((readl(PMCSR(register_base)) & 0x3) == state) {
+ /* Reset First */
+ dc00r.whole = DC_RESET;
+ writel(dc00r.whole, DC00R(register_base));
-+ udelay(10);
-+
++ mdelay(100);
+
+ dc00r.whole = 0xEF2082A;
+ writel(dc00r.whole, DC00R(register_base));
-+ udelay(5);
-+ PRINTK(CHIPNAME ": DC00R = %xx\n", readl(DC00R(register_base)));
++ mdelay(300);
++ PRINTK(CHIPNAME ": DC00R = 0x%08X\n", readl(DC00R(register_base)));
+}
+
+
+ /* MIU interface control 1 */
+ mm00r.whole = 0x4;
+ writel(mm00r.whole, MM00R(register_base));
-+ udelay(5);
++ mdelay(50);
+ writel(0, MM00R(register_base));
-+ udelay(50);
++ mdelay(50);
+
+ /* MIU interface control 2
+ * o PLL 1 output is used as memory clock source.
+ */
-+ mm01r.whole = 0x4143e086;
++ mm01r.whole = 0x4143e086;
+ writel(mm01r.whole, MM01R(register_base));
+
+ /* memory interface control 3 */
+ /* memory interface control 4 */
+ mm03r.whole = 0x1;
+ writel(mm03r.whole, MM03R(register_base));
-+ mdelay(10);
++ mdelay(50);
+
+ /* MIU interface control 1 */
+ mm00r.whole = 0x3;
+ fp0fr.whole = 0xA16c44;
+ writel(fp0fr.whole, FP0FR(addr));
+
-+
+ /* Set them again */
+ fp02r.whole = 0x0;
+ writel(fp02r.whole, FP02R(addr));
+ union pm00r pm00r;
+ union pm01r pm01r;
+ union pm02r pm02r;
-+// union pm06r pm06r;
-+// union pm07r pm07r;
+
+ /* power management miscellaneous control
+ * o GE is driven by PLL 1 clock.
+ /* D2 state control */
+ pm02r.whole = 0x271;
+ writel(pm02r.whole, PM02R(register_base));
-+
-+#if 0
-+ /* PLL 2 programming */
-+ pm06r.whole = 0xE90830;
-+ writel(pm06r.whole, PM06R(register_base));
-+
-+ /* PLL 3 programming */
-+ pm07r.whole = 0xE90830;
-+ writel(pm07r.whole, PM07R(register_base));
-+#endif
+}
+
+/****
-+ * initialize graphics controller 1.
++ * initialize graphics controller 1
++ * and graphics controller 2
+ */
+static void
-+gc1_reset(unsigned long register_base, spinlock_t *lock )
++gc1_gc2_reset(unsigned long register_base, spinlock_t *lock )
+{
+ unsigned long flags;
+ union gc00r gc00r;
+ union gc05r gc05r;
+ union gc08r gc08r;
+ union gc09r gc09r;
-+// union gc0er gc0er;
-+// union gc11r gc11r;
++ union gc0cr gc0cr;
++ union gc0er gc0er;
++ union gc20r gc20r;
++ union gc22r gc22r;
++ union gc23r gc23r;
++ union gc24r gc24r;
++ union gc25r gc25r;
++ union gc28r gc28r;
++ union gc29r gc29r;
++ union gc2cr gc2cr;
++ union gc2er gc2er;
++
+ union pm00r pm00r;
+ union pm06r pm06r;
++ union pm06r pm07r;
+
+ spin_lock_irqsave(lock, flags);
+
-+ /* graphics controller CRT control */
-+ gc01r.whole = 0x800;
-+ writel(gc01r.whole, GC01R(register_base));
++ /* alternate window 1 stride */
++ gc0er.whole = 0x640;
++ writel(gc0er.whole, GC0ER(register_base));
++
++ /* image window 1 start address */
++ gc0cr.whole = 0x0;
++ writel(gc0cr.whole, GC0CR(register_base));
++
++ /* alternate window 2 stride */
++ gc2er.whole = 0x640;
++ writel(gc0er.whole, GC2ER(register_base));
++
++ /* image window 2 start address */
++ gc2cr.whole = 0x0;
++ writel(gc2cr.whole, GC2CR(register_base));
++
++ /* read PM Register */
++ pm00r.whole = readl(PM00R(register_base));
++
++ /* horizontal window 1 control */
++ gc08r.whole = 0x131f0000;
++ writel(gc08r.whole, GC08R(register_base));
++
++ /* vertical window 1 control */
++ gc09r.whole = 0x12570000;
++ writel(gc09r.whole, GC09R(register_base));
+
+ /* horizontal display 1 control */
+ gc02r.whole = 0x320041e;
+ gc05r.whole = 0x25d0259;
+ writel(gc05r.whole, GC05R(register_base));
+
-+ /* horizontal window 1 control */
-+ gc08r.whole = 0x131f0000;
-+ writel(gc08r.whole, GC08R(register_base));
++ /* graphics controller CRT control */
++ gc01r.whole = 0x800;
++ writel(gc01r.whole, GC01R(register_base));
+
-+ /* vertical window 1 control */
-+ gc09r.whole = 0x2570000;
-+ writel(gc09r.whole, GC09R(register_base));
++ /* PLL 2 programming */
++ pm06r.whole = 0xE90830;
++ writel(pm06r.whole, PM06R(register_base));
++
++ /* graphics controller 1 register
++ * o GC1 clock source is PLL 2.
++ * o hardware cursor is disabled.
++ */
++ gc00r.whole = 0x10000C8 | 0x20000;
++ writel(gc00r.whole, GC00R(register_base));
+
+#if 0
+ /* alternate horizontal window 1 control */
+ writel(0x00000000, GC13R(register_base));
+#endif
+
-+ /* PLL 2 programming */
-+ pm06r.whole = 0xE90830;
-+ writel(pm06r.whole, PM06R(register_base));
++ /* horizontal window 2 control */
++ gc28r.whole = 0x31f0000;
++ writel(gc28r.whole, GC28R(register_base));
+
++ /* vertical window 2 control */
++ gc29r.whole = 0x2570000;
++ writel(gc29r.whole, GC29R(register_base));
+
-+ /* graphics controller 1 register
-+ * o GC1 clock source is PLL 2.
++ /* horizontal display 2 control */
++ gc22r.whole = 0x320041e;
++ writel(gc22r.whole, GC22R(register_base));
++
++ /* vertical display 2 control */
++ gc23r.whole = 0x2570273;
++ writel(gc23r.whole, GC23R(register_base));
++
++ /* horizontal sync 2 control */
++ gc24r.whole = 0x3c70347;
++ writel(gc24r.whole, GC24R(register_base));
++
++ /* vertical sync 2 control */
++ gc25r.whole = 0x25d0259;
++ writel(gc25r.whole, GC25R(register_base));
++
++ /* graphics controller CRT control */
++ gc01r.whole = 0x800;
++ writel(gc01r.whole, GC01R(register_base));
++
++ /* PLL 3 programming */
++ pm07r.whole = 0xE90830;
++ writel(pm07r.whole, PM07R(register_base));
++
++ /* graphics controller 2 register
++ * o GC2 clock source is PLL 3.
+ * o hardware cursor is disabled.
+ */
-+ gc00r.whole = 0x10200C8;
-+ writel(gc00r.whole, GC00R(register_base));
++ gc20r.whole = 0x10000C8 | 0x30000;
++ writel(gc20r.whole, GC20R(register_base));
+
+ /*
-+ * Enable PLL2 in the PM Register
++ * Enable PLL2 and PLL3 in the PM Register
+ */
-+ pm00r.whole = readl(PM00R(register_base));
+ pm00r.part.pll2_enbl = 0x1;
++ pm00r.part.pll3_enbl = 0x1;
+ writel(pm00r.whole, PM00R(register_base));
+
+ spin_unlock_irqrestore(lock, flags);
+ writel(0, GE0BR(register_base));
+}
+
-+
+/****
+ * initialize Color Palette 1.
+ */
+}
+
+
-+
-+
+/*
+ * Below functions are called from the skeleton
+ */
+ dc_reset(addr); /* device configuration */
+
+ power_state_transition(addr, 0); /* transition to D0 state */
++
+ pmu_reset(addr); /* power management unit */
++
+ miu_reset(addr); /* memory interface unit */
++
+ ge_reset(addr); /* graphics engine */
++
+ fpctrl_reset(addr); /* reset the panel settings */
-+ gc1_reset(addr, lock); /* graphics controller 1 */
++
++ gc1_gc2_reset(addr, lock); /* graphics controller 1 and 2 */
++
+ cp1_reset(addr); /* color palette 1 */
-+ mq200_external_ondisplay(addr);
++
++ mq200_external_ondisplay(addr); /* LCD and CRT */
+}
+
+void mq200_external_offdisplay(unsigned long addr)
+ /*
+ * Set the framebuffer details
+ */
-+ #warning FIX HERE AS WELL
+ union gc00r gc00r;
++ union gc01r gc01r;
++ union gc20r gc20r;
+ union fp00r fp00r;
++
++ /* enable LCD for GC2 */
++ fp00r.whole = readl(FP00R(addr));
++ fp00r.whole &= 0xfffffffc;
++
++ gc20r.whole = readl(GC20R(addr));
++
++ if(!(gc20r.whole & 0x1)) {
++ gc20r.whole |= 0x1;
++ writel(gc20r.whole, GC20R(addr));
++ }
++
++ fp00r.whole |= 0x3;
++ writel(fp00r.whole, FP00R(addr));
++
++ /* enable CRT for GC1 */
+ gc00r.whole = readl(GC00R(addr));
-+ fp00r.whole = readl(FP00R(addr));
+
+ if(!(gc00r.whole & 0x1)) {
-+ gc00r.whole |= 1;
++ gc00r.whole |= 0x1;
+ writel(gc00r.whole, GC00R(addr));
+ }
++
++ gc01r.whole = readl(GC01R(addr));
++ gc01r.whole &= 0xfffffffc;
+
-+ fp00r.whole |= 0x01;
-+ writel(fp00r.whole, FP00R(addr));
++ gc01r.whole |= 0x1;
++ writel(gc01r.whole, GC01R(addr));
++
+}
+
+int mq200_external_probe(unsigned long addr)
+ return 0;
+
+ pc00r.whole = readl(PC00R(addr));
-+ printk(KERN_INFO "mq200 video driver found Vendor:%d Device:%d\n",
++ printk(KERN_INFO "mq200 video driver found Vendor: 0x%X Device: 0x%X\n",
+ pc00r.part.device, pc00r.part.vendor);
+ return 1;
+}
diff -uNr linux-2.6.20.vanilla/drivers/video/mq200/mq_skeleton.c linux-2.6.20/drivers/video/mq200/mq_skeleton.c
--- linux-2.6.20.vanilla/drivers/video/mq200/mq_skeleton.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.20/drivers/video/mq200/mq_skeleton.c 2007-02-11 16:41:09.000000000 +0100
-@@ -0,0 +1,401 @@
++++ linux-2.6.20/drivers/video/mq200/mq_skeleton.c 2007-03-28 22:53:44.000000000 +0200
+@@ -0,0 +1,398 @@
+/*
+ * Author: Holger Hans Peter Freyther
+ *
+}
+
+
-+
-+
+static struct fb_ops mq200_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = mq200_check_var,
+ if(!mq200_external_probe(info->io_regions.virt_mmio_base))
+ goto error_out;
+
-+
++ GPDR |= (1<<3);
+ GAFR &= ~(1<<3);
+ GPSR |= (1<<3);
-+ GPDR |= (1<<3);
+
+ mq200_external_setqmode(&info->monitor_info,
+ info->io_regions.virt_mmio_base,
git.openpandora.org / openembedded.git / commitdiff