drm/i915: Broadwell expands ACTHD to 64bit

As Broadwell has an increased virtual address size, it requires more
than 32 bits to store offsets into its address space. This includes the
debug registers to track the current HEAD of the individual rings, which
may be anywhere within the per-process address spaces. In order to find
the full location, we need to read the high bits from a second register.
We then also need to expand our storage to keep track of the larger
address.

v2: Carefully read the two registers to catch wraparound between
    the reads.
v3: Use a WARN_ON rather than loop indefinitely on an unstable
    register read.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Timo Aaltonen <tjaalton@ubuntu.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Drop spurious hunk which conflicted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7b344c5300f0ee9b24ec4c69273286d5d773f4d8..537404b9f7604a5a0891909174f66b811d941335 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -351,12 +351,12 @@ struct drm_i915_error_state {
                u32 ipeir;
                u32 ipehr;
                u32 instdone;
-               u32 acthd;
                u32 bbstate;
                u32 instpm;
                u32 instps;
                u32 seqno;
                u64 bbaddr;
+               u64 acthd;
                u32 fault_reg;
                u32 faddr;
                u32 rc_psmi; /* sleep state */
@@ -2746,6 +2746,17 @@ void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
 #define I915_READ64(reg)       dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
 
+#define I915_READ64_2x32(lower_reg, upper_reg) ({                      \
+               u32 upper = I915_READ(upper_reg);                       \
+               u32 lower = I915_READ(lower_reg);                       \
+               u32 tmp = I915_READ(upper_reg);                         \
+               if (upper != tmp) {                                     \
+                       upper = tmp;                                    \
+                       lower = I915_READ(lower_reg);                   \
+                       WARN_ON(I915_READ(upper_reg) != upper);         \
+               }                                                       \
+               (u64)upper << 32 | lower; })
+
 #define POSTING_READ(reg)      (void)I915_READ_NOTRACE(reg)
 #define POSTING_READ16(reg)    (void)I915_READ16_NOTRACE(reg)
 

diff --cc drivers/gpu/drm/i915/i915_gpu_error.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_irq.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_reg.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_ringbuffer.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_ringbuffer.h
Simple merge