rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASK
authorPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fri, 1 Dec 2017 23:19:14 +0000 (00:19 +0100)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fri, 1 Dec 2017 23:27:42 +0000 (00:27 +0100)
The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15.
Fix this to remove an "integer-overflow on shifted constant" warning.

Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
arch/arm/include/asm/arch-rockchip/cru_rk3128.h

index 3d8317e..90012c7 100644 (file)
@@ -187,7 +187,7 @@ enum {
        DCLK_VOP_SEL_MASK          = 1 << DCLK_VOP_SEL_SHIFT,
        DCLK_VOP_PLL_SEL_CPLL           = 0,
        DCLK_VOP_DIV_CON_SHIFT          = 8,
-       DCLK_VOP_DIV_CON_MASK           = 0xfff << DCLK_VOP_DIV_CON_SHIFT,
+       DCLK_VOP_DIV_CON_MASK           = 0xff << DCLK_VOP_DIV_CON_SHIFT,
 
        /* CRU_CLKSEL31_CON */
        VIO0_PLL_SHIFT          = 5,