export KDIR=$(KERNELDIR)
export BUILD = release
+export TI_PLATFORM ?= omap3
+export OMAPES ?= 3.x
export KBUILD_EXTRA_SYMBOLS = `pwd`/services4/srvkm/env/linux/kbuild/Module.symvers
#if !defined(NO_HARDWARE) && \
defined(SYS_USING_INTERRUPTS) && \
- defined(SGX530) && (SGX_CORE_REV == 125)
+ defined(SGX530) // && (SGX_CORE_REV == 125)
#define SGX_OCP_REGS_ENABLED
#endif
{
PVRSRV_ERROR eError = EnableSGXClocks(psSysData);
- if(eError == PVRSRV_OK)
+ if(cpu_is_omap3630() && eError == PVRSRV_OK)
{
OSWriteHWReg(gpvOCPRegsLinAddr,
EUR_CR_OCP_DEBUG_CONFIG - EUR_CR_OCP_REVISION,
#if !defined(SGX_DYNAMIC_TIMING_INFO)
psTimingInfo = &gsSGXDeviceMap.sTimingInfo;
- psTimingInfo->ui32CoreClockSpeed = SYS_SGX_CLOCK_SPEED;
+ psTimingInfo->ui32CoreClockSpeed = cpu_is_omap3630() ? 200000000 : 110666666;
psTimingInfo->ui32HWRecoveryFreq = SYS_SGX_HWRECOVERY_TIMEOUT_FREQ;
#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT)
psTimingInfo->bEnableActivePM = IMG_TRUE;
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LOCATEDEV);
#if defined(SGX_OCP_REGS_ENABLED)
+ if (cpu_is_omap3630())
{
IMG_SYS_PHYADDR sOCPRegsSysPBase;
IMG_CPU_PHYADDR sOCPRegsCpuPBase;
}
#if defined(SGX_OCP_REGS_ENABLED)
- OSUnMapPhysToLin(gpvOCPRegsLinAddr,
+ if (cpu_is_omap3630())
+ OSUnMapPhysToLin(gpvOCPRegsLinAddr,
SYS_OMAP3430_OCP_REGS_SIZE,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
#define SYS_OMAP3430_SGX_REGS_SYS_PHYS_BASE 0x50000000
-#define SYS_OMAP3430_SGX_REGS_SIZE 0x4000
+#define SYS_OMAP3430_SGX_REGS_SIZE 0x10000
#define SYS_OMAP3430_SGX_IRQ 21
#define SGX_PARENT_CLOCK "core_ck"
#endif
+#undef SYS_SGX_CLOCK_SPEED
+#define SYS_SGX_CLOCK_SPEED sgx_clock_speed
+static int sgx_clock_speed;
+
#if !defined(PDUMP) && !defined(NO_HARDWARE)
static IMG_BOOL PowerLockWrappedOnCPU(SYS_SPECIFIC_DATA *psSysSpecData)
{
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: SGX Functional Clock is %dMhz", HZ_TO_MHZ(rate)));
}
#endif
+#if 1
+ {
+ static int logged;
+ IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK);
+ if (!logged) {
+ printk(KERN_INFO "SGX clock rate: %u\n", rate);
+ logged = 1;
+ }
+ }
+#endif
atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
{
bPowerLock = IMG_FALSE;
+ sgx_clock_speed = cpu_is_omap3630() ? 200000000 : 110666666;
+
spin_lock_init(&psSysSpecData->sPowerLock);
atomic_set(&psSysSpecData->sPowerLockCPU, -1);
spin_lock_init(&psSysSpecData->sNotifyLock);
#define SGX_PARENT_CLOCK "core_ck"
#endif
+#undef SYS_SGX_CLOCK_SPEED
+#define SYS_SGX_CLOCK_SPEED sgx_clock_speed
+static int sgx_clock_speed;
+
static PVRSRV_ERROR PowerLockWrap(SYS_SPECIFIC_DATA *psSysSpecData, IMG_BOOL bTryLock)
{
if (!in_interrupt())
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: SGX Functional Clock is %dMhz", HZ_TO_MHZ(rate)));
}
#endif
+#if 1
+ {
+ static int logged;
+ IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK);
+ if (!logged) {
+ printk(KERN_INFO "SGX clock rate: %u\n", rate);
+ logged = 1;
+ }
+ }
+#endif
atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
+ SYS_SGX_CLOCK_SPEED = cpu_is_omap3630() ? 200000000 : 110666666;
+
psCLK = clk_get(NULL, SGX_PARENT_CLOCK);
if (IS_ERR(psCLK))
{