tile: remove homegrown L1_CACHE_ALIGN macro

Let's use the standard L1_CACHE_ALIGN macro instead.

Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>

diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
index c2b7dcf..ee59714 100644 (file)
--- a/arch/tile/include/asm/cache.h
+++ b/arch/tile/include/asm/cache.h
@@ -20,7 +20,6 @@
 /* bytes per L1 data cache line */
 #define L1_CACHE_SHIFT         CHIP_L1D_LOG_LINE_SIZE()
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
-#define L1_CACHE_ALIGN(x)      (((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES)
 
 /* bytes per L1 instruction cache line */
 #define L1I_CACHE_SHIFT                CHIP_L1I_LOG_LINE_SIZE()