+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_TREE_PREEMPT_RCU=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_KALLSYMS is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_LBDAF is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_OMAP_MBOX_FWK=m
-CONFIG_MACH_AMS_DELTA=y
-CONFIG_OMAP_ARM_150MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=/dev/ram0 initrd=0x11c00000,4M"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-# CONFIG_SUSPEND is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IPV6=y
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_AMS_DELTA=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_CATC=y
-CONFIG_USB_KAWETH=y
-CONFIG_USB_PEGASUS=y
-CONFIG_USB_RTL8150=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_OMAP=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_OMAP_SOC=y
-CONFIG_SND_OMAP_SOC_AMS_DELTA=y
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_AMS_DELTA=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_NFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_ARCH_OMAP850=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_MACH_HERALD=y
-CONFIG_OMAP_ARM_195MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-CONFIG_CPU_ARM925T=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200 ip=dhcp"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=m
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_ZLIB=y
-CONFIG_CRYPTO_LZO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_MUX is not set
-CONFIG_OMAP_MBOX_FWK=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_NOKIA770=y
-CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
-CONFIG_OMAP_ARM_216MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=1f03 rootfstype=jffs2 time"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_CONNECTOR=y
-# CONFIG_PROC_EVENTS is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_TUN=y
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_USBNET=y
-# CONFIG_USB_NET_AX8817X is not set
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_PPP=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP_UWIRE=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_OMAP=y
-CONFIG_FB_OMAP_LCDC_EXTERNAL=y
-CONFIG_FB_OMAP_LCDC_HWA742=y
-CONFIG_FB_OMAP_MANUAL_UPDATE=y
-CONFIG_FB_OMAP_LCD_MIPID=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-CONFIG_SND_DUMMY=y
-CONFIG_SND_USB_AUDIO=y
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_SUSPEND=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_CONSOLE=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_FILE_STORAGE_TEST=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_SECURITY=y
--- /dev/null
+CONFIG_EXPERIMENTAL=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_IKCONFIG=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_ELF_CORE is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_SHMEM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLOB=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP1=y
+CONFIG_OMAP_RESET_CLOCKS=y
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MBOX_FWK=y
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_ARCH_OMAP730=y
+CONFIG_ARCH_OMAP850=y
+CONFIG_ARCH_OMAP16XX=y
+CONFIG_MACH_OMAP_INNOVATOR=y
+CONFIG_MACH_OMAP_H2=y
+CONFIG_MACH_OMAP_H3=y
+CONFIG_MACH_OMAP_HTCWIZARD=y
+CONFIG_MACH_HERALD=y
+CONFIG_MACH_OMAP_OSK=y
+CONFIG_MACH_OMAP_PERSEUS2=y
+CONFIG_MACH_OMAP_FSAMPLE=y
+CONFIG_MACH_VOICEBLUE=y
+CONFIG_MACH_OMAP_PALMTE=y
+CONFIG_MACH_OMAP_PALMZ71=y
+CONFIG_MACH_OMAP_PALMTT=y
+CONFIG_MACH_SX1=y
+CONFIG_MACH_NOKIA770=y
+CONFIG_MACH_AMS_DELTA=y
+CONFIG_MACH_OMAP_GENERIC=y
+CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
+CONFIG_OMAP_ARM_216MHZ=y
+CONFIG_OMAP_ARM_195MHZ=y
+CONFIG_OMAP_ARM_192MHZ=y
+CONFIG_OMAP_ARM_182MHZ=y
+CONFIG_OMAP_ARM_168MHZ=y
+# CONFIG_OMAP_ARM_60MHZ is not set
+# CONFIG_ARM_THUMB is not set
+CONFIG_PCCARD=y
+CONFIG_OMAP_CF=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_LEDS=y
+CONFIG_LEDS_CPU=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=1f03 rootfstype=jffs2"
+CONFIG_FPE_NWFPE=y
+CONFIG_BINFMT_MISC=y
+CONFIG_PM=y
+# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+CONFIG_NETFILTER=y
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_CONNECTOR=y
+# CONFIG_PROC_EVENTS is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=3
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_NAND=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_IDE=m
+CONFIG_BLK_DEV_IDECS=m
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_PHYLIB=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMC91X=y
+CONFIG_USB_CATC=y
+CONFIG_USB_KAWETH=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_RTL8150=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_SLIP=y
+CONFIG_SLIP_COMPRESSED=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SPI_OMAP_UWIRE=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_OMAP_WATCHDOG=y
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_VIRTUAL=y
+CONFIG_FB_OMAP=y
+CONFIG_FB_OMAP_LCDC_EXTERNAL=y
+CONFIG_FB_OMAP_LCDC_HWA742=y
+CONFIG_FB_OMAP_MANUAL_UPDATE=y
+CONFIG_FB_OMAP_LCD_MIPID=y
+CONFIG_FB_OMAP_BOOTLOADER_INIT=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_6x11=y
+CONFIG_FONT_MINI_4x6=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+CONFIG_SND_DUMMY=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+# CONFIG_USB_HID is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_TEST=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETH=m
+# CONFIG_USB_ETH_RNDIS is not set
+CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_FILE_STORAGE_TEST=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_OMAP=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_OMAP=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=866
+CONFIG_FAT_DEFAULT_IOCHARSET="koi8-r"
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_CRAMFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_UTF8=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_SECURITY=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_ZLIB=y
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_LIBCRC32C=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_OMAP_ARM_168MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS2,115200 root=0803 ro init=/bin/sh"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_RTL8150=y
-CONFIG_USB_USBNET=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_OMAP_ARM_192MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS2,115200 root=0803 ro init=/bin/sh"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_RTL8150=y
-CONFIG_USB_USBNET=y
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-# CONFIG_OMAP_MUX is not set
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_OMAP_ARM_192MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=tty0 console=ttyS2,115200 root=0801"
-CONFIG_FPE_NWFPE=y
-CONFIG_ARTHUR=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_USBNET=y
-CONFIG_USB_ALI_M5632=y
-# CONFIG_USB_BELKIN is not set
-# CONFIG_USB_ARMLINUX is not set
-CONFIG_PPP=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_VIDEO_OUTPUT_CONTROL=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_PCBC=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_OMAP_MUX_DEBUG=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_OMAP_H2=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=/dev/ram0 rw initrd=0x10600000,8M ramdisk_size=8192"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEBUG_DRIVER=y
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=3
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_PPP=y
-CONFIG_SLIP=y
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_EVBUG=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP_UWIRE=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_SUSPEND=y
-CONFIG_USB_OTG=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_TEST=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_MACH_OMAP_INNOVATOR=y
-CONFIG_OMAP_ARM_168MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-CONFIG_PREEMPT=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200n8 root=/dev/nfs ip=bootp noinitrd"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_USB_RTL8150=y
-CONFIG_USB_USBNET=y
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_OMAP_INNOVATOR=y
-CONFIG_OMAP_ARM_192MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_CPU_DCACHE_WRITETHROUGH=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=tty0 console=ttyS0,115200 initrd=0x10200000,8M root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_OMAP_RESET_CLOCKS=y
-CONFIG_OMAP_32K_TIMER=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_OMAP_OSK=y
-CONFIG_OMAP_ARM_192MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_PCCARD=y
-CONFIG_OMAP_CF=y
-CONFIG_NO_HZ=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x10400000,8M root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_IDE=m
-CONFIG_BLK_DEV_IDECS=m
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_ISO8859_1=m
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_ARCH_OMAP730=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_MACH_OMAP_PERSEUS2=y
-CONFIG_OMAP_ARM_182MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_PREEMPT=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200 ip=dhcp"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_VIRTUAL=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_MACH_OMAP_PALMTE=y
-CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=850
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_CRC_CCITT=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_MACH_OMAP_PALMTT=y
-CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/mmcblk0p2 rw init=/init"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SPI=y
-CONFIG_SPI_OMAP_UWIRE=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_OMAP=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_LIBCRC32C=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="-z71"
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_MACH_OMAP_PALMZ71=y
-CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=16
-CONFIG_SPI=y
-CONFIG_SPI_OMAP_UWIRE=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_OMAP=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_LIBCRC32C=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EMBEDDED=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_BASE_FULL is not set
-# CONFIG_SHMEM is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_SLOB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_OMAP_MBOX_FWK=y
-CONFIG_MACH_SX1=y
-CONFIG_OMAP_ARM_168MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_CONNECTOR=y
-# CONFIG_PROC_EVENTS is not set
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_RAM=m
-CONFIG_BLK_DEV_RAM_COUNT=2
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_OMAP=y
-CONFIG_FB_OMAP_BOOTLOADER_INIT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=866
-CONFIG_FAT_DEFAULT_IOCHARSET="koi8-r"
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_866=y
-CONFIG_NLS_CODEPAGE_1251=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_5=y
-CONFIG_NLS_KOI8_R=y
-CONFIG_NLS_UTF8=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_LIBCRC32C=y
*
*/
#ifndef __arch_ioremap
-#define ioremap(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE)
-#define ioremap_nocache(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE)
-#define ioremap_cached(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_CACHED)
-#define ioremap_wc(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_WC)
-#define iounmap(cookie) __iounmap(cookie)
-#else
+#define __arch_ioremap __arm_ioremap
+#define __arch_iounmap __iounmap
+#endif
+
#define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
#define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
#define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
#define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC)
-#define iounmap(cookie) __arch_iounmap(cookie)
-#endif
+#define iounmap __arch_iounmap
/*
* io{read,write}{8,16,32} macros
#define __mem_isa(a) (a)
#ifndef __ASSEMBLER__
-#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t)
-#define __arch_iounmap(v) davinci_iounmap(v)
+#define __arch_ioremap davinci_ioremap
+#define __arch_iounmap davinci_iounmap
void __iomem *davinci_ioremap(unsigned long phys, size_t size,
unsigned int type);
extern size_t iop13xx_atue_mem_size;
extern size_t iop13xx_atux_mem_size;
-#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
-#define __arch_iounmap(a) __iop13xx_iounmap(a)
+#define __arch_ioremap __iop13xx_ioremap
+#define __arch_iounmap __iop13xx_iounmap
#endif
#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
#define __mem_pci(a) (a)
-#define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
-#define __arch_iounmap(a) __iop3xx_iounmap(a)
+#define __arch_ioremap __iop3xx_ioremap
+#define __arch_iounmap __iop3xx_iounmap
#endif
#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
#define __mem_pci(a) (a)
-#define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
-#define __arch_iounmap(a) __iop3xx_iounmap(a)
+#define __arch_ioremap __iop3xx_ioremap
+#define __arch_iounmap __iop3xx_iounmap
#endif
__iounmap(addr);
}
-#define __arch_ioremap(a,s,f) ixp23xx_ioremap(a,s,f)
-#define __arch_iounmap(a) ixp23xx_iounmap(a)
+#define __arch_ioremap ixp23xx_ioremap
+#define __arch_iounmap ixp23xx_iounmap
#endif
__iounmap(addr);
}
-#define __arch_ioremap(a, s, f) __indirect_ioremap(a, s, f)
-#define __arch_iounmap(a) __indirect_iounmap(a)
+#define __arch_ioremap __indirect_ioremap
+#define __arch_iounmap __indirect_iounmap
#define writeb(v, p) __indirect_writeb(v, p)
#define writew(v, p) __indirect_writew(v, p)
__iounmap(addr);
}
-#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
-#define __arch_iounmap(a) __arch_iounmap(a)
+#define __arch_ioremap __arch_ioremap
+#define __arch_iounmap __arch_iounmap
#define __io(a) __io(a)
#define __mem_pci(a) (a)
config MACH_AMS_DELTA
bool "Amstrad E3 (Delta)"
depends on ARCH_OMAP1 && ARCH_OMAP15XX
+ select FIQ
help
Support for the Amstrad E3 (codename Delta) videophone. Say Y here
if you have such a device.
-config AMS_DELTA_FIQ
- bool "Fast Interrupt Request (FIQ) support for the E3"
- depends on MACH_AMS_DELTA
- select FIQ
- help
- Provide a FIQ handler for the E3.
- This allows for fast handling of interrupts generated
- by the clock line of the E3 mailboard (or a PS/2 keyboard)
- connected to the GPIO based external keyboard port.
-
config MACH_OMAP_GENERIC
bool "Generic OMAP board"
depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o
obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o
obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o
-obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o
-obj-$(CONFIG_AMS_DELTA_FIQ) += ams-delta-fiq.o ams-delta-fiq-handler.o
+obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o ams-delta-fiq.o \
+ ams-delta-fiq-handler.o
obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o
obj-$(CONFIG_MACH_HERALD) += board-htcherald.o
obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o
endif
+# GPIO
+obj-$(CONFIG_ARCH_OMAP730) += gpio7xx.o
+obj-$(CONFIG_ARCH_OMAP850) += gpio7xx.o
+obj-$(CONFIG_ARCH_OMAP15XX) += gpio15xx.o
+obj-$(CONFIG_ARCH_OMAP16XX) += gpio16xx.o
+
# LEDs support
led-$(CONFIG_MACH_OMAP_H2) += leds-h2p2-debug.o
led-$(CONFIG_MACH_OMAP_H3) += leds-h2p2-debug.o
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <plat/io.h>
#include <plat/board-ams-delta.h>
#include <mach/gpio.h>
#include <plat/keypad.h>
{
omap1_init_common_hw();
omap_init_irq();
- omap_gpio_init();
}
static struct map_desc ams_delta_io_desc[] __initdata = {
#endif
platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
-#ifdef CONFIG_AMS_DELTA_FIQ
ams_delta_init_fiq();
-#endif
omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
}
static struct plat_serial8250_port ams_delta_modem_ports[] = {
{
- .membase = (void *) AMS_DELTA_MODEM_VIRT,
+ .membase = IOMEM(AMS_DELTA_MODEM_VIRT),
.mapbase = AMS_DELTA_MODEM_PHYS,
.irq = -EINVAL, /* changed later */
.flags = UPF_BOOT_AUTOCONF,
{
int err;
+ if (!machine_is_ams_delta())
+ return -ENODEV;
+
omap_cfg_reg(M14_1510_GPIO2);
ams_delta_modem_ports[0].irq =
gpio_to_irq(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
},
};
+static void __init fsample_init_smc91x(void)
+{
+ fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
+ mdelay(50);
+ fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
+ H2P2_DBG_FPGA_LAN_RESET);
+ mdelay(50);
+}
+
static struct mtd_partition nor_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
static void __init omap_fsample_init(void)
{
+ fsample_init_smc91x();
+
if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
BUG();
gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
omap_register_i2c_bus(1, 100, NULL, 0);
}
-static void __init fsample_init_smc91x(void)
-{
- fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
- fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
- H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
-}
-
static void __init omap_fsample_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
- omap_gpio_init();
- fsample_init_smc91x();
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
{
omap1_init_common_hw();
omap_init_irq();
- omap_gpio_init();
- h2_init_smc91x();
}
static struct omap_usb_config h2_usb_config __initdata = {
static void __init h2_init(void)
{
+ h2_init_smc91x();
+
/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
* to address 0 by a dip switch), NAND on CS2B. The NAND driver will
* notice whether a NAND chip is enabled at probe time.
.resource = smc91x_resources,
};
+static void __init h3_init_smc91x(void)
+{
+ omap_cfg_reg(W15_1710_GPIO40);
+ if (gpio_request(40, "SMC91x irq") < 0) {
+ printk("Error requesting gpio 40 for smc91x irq\n");
+ return;
+ }
+}
+
#define GPTIMER_BASE 0xFFFB1400
#define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800))
#define GPTIMER_REGS_SIZE 0x46
static void __init h3_init(void)
{
+ h3_init_smc91x();
+
/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
* to address 0 by a dip switch), NAND on CS2B. The NAND driver will
* notice whether a NAND chip is enabled at probe time.
h3_mmc_init();
}
-static void __init h3_init_smc91x(void)
-{
- omap_cfg_reg(W15_1710_GPIO40);
- if (gpio_request(40, "SMC91x irq") < 0) {
- printk("Error requesting gpio 40 for smc91x irq\n");
- return;
- }
-}
-
static void __init h3_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
- omap_gpio_init();
- h3_init_smc91x();
}
static void __init h3_map_io(void)
.keep_vref_on = 1,
.x_plate_ohms = 496,
.gpio_pendown = HTCHERALD_GPIO_TS,
- .pressure_max = 100000,
+ .pressure_max = 10000,
.pressure_min = 5000,
.x_min = 528,
.x_max = 3760,
printk(KERN_INFO "HTC Herald init.\n");
/* Do board initialization before we register all the devices */
- omap_gpio_init();
-
omap_board_config = htcherald_config;
omap_board_config_size = ARRAY_SIZE(htcherald_config);
platform_add_devices(devices, ARRAY_SIZE(devices));
{
omap1_init_common_hw();
omap_init_irq();
- omap_gpio_init();
-#ifdef CONFIG_ARCH_OMAP15XX
- if (cpu_is_omap1510()) {
- omap1510_fpga_init_irq();
- }
-#endif
- innovator_init_smc91x();
}
#ifdef CONFIG_ARCH_OMAP15XX
static void __init innovator_init(void)
{
+ if (cpu_is_omap1510())
+ omap1510_fpga_init_irq();
+ innovator_init_smc91x();
+
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
unsigned char reg;
platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
spi_register_board_info(nokia770_spi_board_info,
ARRAY_SIZE(nokia770_spi_board_info));
- omap_gpio_init();
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
hwa742_dev_init();
{
omap1_init_common_hw();
omap_init_irq();
- omap_gpio_init();
- osk_init_smc91x();
- osk_init_cf();
}
static struct omap_usb_config osk_usb_config __initdata = {
{
u32 l;
+ osk_init_smc91x();
+ osk_init_cf();
+
/* Workaround for wrong CS3 (NOR flash) timing
* There are some U-Boot versions out there which configure
* wrong CS3 memory timings. This mainly leads to CRC
{
omap1_init_common_hw();
omap_init_irq();
- omap_gpio_init();
}
static const int palmte_keymap[] = {
{
omap1_init_common_hw();
omap_init_irq();
- omap_gpio_init();
}
static int palmz71_keymap[] = {
{ OMAP_TAG_LCD, &perseus2_lcd_config },
};
+static void __init perseus2_init_smc91x(void)
+{
+ fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
+ mdelay(50);
+ fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
+ H2P2_DBG_FPGA_LAN_RESET);
+ mdelay(50);
+}
+
static void __init omap_perseus2_init(void)
{
+ perseus2_init_smc91x();
+
if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
BUG();
gpio_direction_input(P2_NAND_RB_GPIO_PIN);
omap_register_i2c_bus(1, 100, NULL, 0);
}
-static void __init perseus2_init_smc91x(void)
-{
- fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
- fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
- H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
-}
-
static void __init omap_perseus2_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
- omap_gpio_init();
- perseus2_init_smc91x();
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc omap_perseus2_io_desc[] __initdata = {
{
omap1_init_common_hw();
omap_init_irq();
- omap_gpio_init();
}
/*----------------------------------------*/
static int __init ext_uart_init(void)
{
+ if (!machine_is_voiceblue())
+ return -ENODEV;
+
return platform_device_register(&serial_device);
}
arch_initcall(ext_uart_init);
{
omap1_init_common_hw();
omap_init_irq();
- omap_gpio_init();
}
static void __init voiceblue_init(void)
static int __init voiceblue_setup(void)
{
+ if (!machine_is_voiceblue())
+ return -ENODEV;
+
/* Setup panic notifier */
atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
* activation. [ GPIO code for 1510 ]
*/
static struct clk arm_gpio_ck = {
- .name = "arm_gpio_ck",
+ .name = "ick",
.ops = &clkops_generic,
.parent = &ck_dpll1,
.flags = ENABLE_ON_INIT,
CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
- CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310),
+ CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
/* Virtual clocks */
CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
- CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
- CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX),
- CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
+ CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+ CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
+ CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
#include <linux/io.h>
#include <linux/spi/spi.h>
+#include <mach/camera.h>
#include <mach/hardware.h>
#include <asm/mach/map.h>
*/
static int __init omap1_init_devices(void)
{
+ if (!cpu_class_is_omap1())
+ return -ENODEV;
+
/* please keep these calls, and their implementations above,
* in alphabetical order so they're easier to sort through.
*/
#include <plat/io.h>
#include <plat/tc.h>
+#include <plat/flash.h>
void omap1_set_vpp(struct map_info *map, int enable)
{
*/
void omap1510_fpga_init_irq(void)
{
- int i;
+ int i, res;
__raw_writeb(0, OMAP1510_FPGA_IMR_LO);
__raw_writeb(0, OMAP1510_FPGA_IMR_HI);
* NOTE: For general GPIO/MPUIO access and interrupts, please see
* gpio.[ch]
*/
- gpio_request(13, "FPGA irq");
+ res = gpio_request(13, "FPGA irq");
+ if (res) {
+ pr_err("%s failed to get gpio\n", __func__);
+ return;
+ }
gpio_direction_input(13);
set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
}
-
-EXPORT_SYMBOL(omap1510_fpga_init_irq);
--- /dev/null
+/*
+ * OMAP15xx specific gpio init
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author:
+ * Charulatha V <charu@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+
+#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
+#define OMAP1510_GPIO_BASE 0xFFFCE000
+
+/* gpio1 */
+static struct __initdata resource omap15xx_mpu_gpio_resources[] = {
+ {
+ .start = OMAP1_MPUIO_VBASE,
+ .end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_MPUIO,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
+ .virtual_irq_start = IH_MPUIO_BASE,
+ .bank_type = METHOD_MPUIO,
+ .bank_width = 16,
+ .bank_stride = 1,
+};
+
+static struct __initdata platform_device omap15xx_mpu_gpio = {
+ .name = "omap_gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &omap15xx_mpu_gpio_config,
+ },
+ .num_resources = ARRAY_SIZE(omap15xx_mpu_gpio_resources),
+ .resource = omap15xx_mpu_gpio_resources,
+};
+
+/* gpio2 */
+static struct __initdata resource omap15xx_gpio_resources[] = {
+ {
+ .start = OMAP1510_GPIO_BASE,
+ .end = OMAP1510_GPIO_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_GPIO_BANK1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
+ .virtual_irq_start = IH_GPIO_BASE,
+ .bank_type = METHOD_GPIO_1510,
+ .bank_width = 16,
+};
+
+static struct __initdata platform_device omap15xx_gpio = {
+ .name = "omap_gpio",
+ .id = 1,
+ .dev = {
+ .platform_data = &omap15xx_gpio_config,
+ },
+ .num_resources = ARRAY_SIZE(omap15xx_gpio_resources),
+ .resource = omap15xx_gpio_resources,
+};
+
+/*
+ * omap15xx_gpio_init needs to be done before
+ * machine_init functions access gpio APIs.
+ * Hence omap15xx_gpio_init is a postcore_initcall.
+ */
+static int __init omap15xx_gpio_init(void)
+{
+ if (!cpu_is_omap15xx())
+ return -EINVAL;
+
+ platform_device_register(&omap15xx_mpu_gpio);
+ platform_device_register(&omap15xx_gpio);
+
+ gpio_bank_count = 2;
+ return 0;
+}
+postcore_initcall(omap15xx_gpio_init);
--- /dev/null
+/*
+ * OMAP16xx specific gpio init
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author:
+ * Charulatha V <charu@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+
+#define OMAP1610_GPIO1_BASE 0xfffbe400
+#define OMAP1610_GPIO2_BASE 0xfffbec00
+#define OMAP1610_GPIO3_BASE 0xfffbb400
+#define OMAP1610_GPIO4_BASE 0xfffbbc00
+#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
+
+/* mpu gpio */
+static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
+ {
+ .start = OMAP1_MPUIO_VBASE,
+ .end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_MPUIO,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
+ .virtual_irq_start = IH_MPUIO_BASE,
+ .bank_type = METHOD_MPUIO,
+ .bank_width = 16,
+ .bank_stride = 1,
+};
+
+static struct __initdata platform_device omap16xx_mpu_gpio = {
+ .name = "omap_gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &omap16xx_mpu_gpio_config,
+ },
+ .num_resources = ARRAY_SIZE(omap16xx_mpu_gpio_resources),
+ .resource = omap16xx_mpu_gpio_resources,
+};
+
+/* gpio1 */
+static struct __initdata resource omap16xx_gpio1_resources[] = {
+ {
+ .start = OMAP1610_GPIO1_BASE,
+ .end = OMAP1610_GPIO1_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_GPIO_BANK1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
+ .virtual_irq_start = IH_GPIO_BASE,
+ .bank_type = METHOD_GPIO_1610,
+ .bank_width = 16,
+};
+
+static struct __initdata platform_device omap16xx_gpio1 = {
+ .name = "omap_gpio",
+ .id = 1,
+ .dev = {
+ .platform_data = &omap16xx_gpio1_config,
+ },
+ .num_resources = ARRAY_SIZE(omap16xx_gpio1_resources),
+ .resource = omap16xx_gpio1_resources,
+};
+
+/* gpio2 */
+static struct __initdata resource omap16xx_gpio2_resources[] = {
+ {
+ .start = OMAP1610_GPIO2_BASE,
+ .end = OMAP1610_GPIO2_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_1610_GPIO_BANK2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
+ .virtual_irq_start = IH_GPIO_BASE + 16,
+ .bank_type = METHOD_GPIO_1610,
+ .bank_width = 16,
+};
+
+static struct __initdata platform_device omap16xx_gpio2 = {
+ .name = "omap_gpio",
+ .id = 2,
+ .dev = {
+ .platform_data = &omap16xx_gpio2_config,
+ },
+ .num_resources = ARRAY_SIZE(omap16xx_gpio2_resources),
+ .resource = omap16xx_gpio2_resources,
+};
+
+/* gpio3 */
+static struct __initdata resource omap16xx_gpio3_resources[] = {
+ {
+ .start = OMAP1610_GPIO3_BASE,
+ .end = OMAP1610_GPIO3_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_1610_GPIO_BANK3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
+ .virtual_irq_start = IH_GPIO_BASE + 32,
+ .bank_type = METHOD_GPIO_1610,
+ .bank_width = 16,
+};
+
+static struct __initdata platform_device omap16xx_gpio3 = {
+ .name = "omap_gpio",
+ .id = 3,
+ .dev = {
+ .platform_data = &omap16xx_gpio3_config,
+ },
+ .num_resources = ARRAY_SIZE(omap16xx_gpio3_resources),
+ .resource = omap16xx_gpio3_resources,
+};
+
+/* gpio4 */
+static struct __initdata resource omap16xx_gpio4_resources[] = {
+ {
+ .start = OMAP1610_GPIO4_BASE,
+ .end = OMAP1610_GPIO4_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_1610_GPIO_BANK4,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
+ .virtual_irq_start = IH_GPIO_BASE + 48,
+ .bank_type = METHOD_GPIO_1610,
+ .bank_width = 16,
+};
+
+static struct __initdata platform_device omap16xx_gpio4 = {
+ .name = "omap_gpio",
+ .id = 4,
+ .dev = {
+ .platform_data = &omap16xx_gpio4_config,
+ },
+ .num_resources = ARRAY_SIZE(omap16xx_gpio4_resources),
+ .resource = omap16xx_gpio4_resources,
+};
+
+static struct __initdata platform_device * omap16xx_gpio_dev[] = {
+ &omap16xx_mpu_gpio,
+ &omap16xx_gpio1,
+ &omap16xx_gpio2,
+ &omap16xx_gpio3,
+ &omap16xx_gpio4,
+};
+
+/*
+ * omap16xx_gpio_init needs to be done before
+ * machine_init functions access gpio APIs.
+ * Hence omap16xx_gpio_init is a postcore_initcall.
+ */
+static int __init omap16xx_gpio_init(void)
+{
+ int i;
+
+ if (!cpu_is_omap16xx())
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
+ platform_device_register(omap16xx_gpio_dev[i]);
+
+ gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
+
+ return 0;
+}
+postcore_initcall(omap16xx_gpio_init);
--- /dev/null
+/*
+ * OMAP7xx specific gpio init
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author:
+ * Charulatha V <charu@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+
+#define OMAP7XX_GPIO1_BASE 0xfffbc000
+#define OMAP7XX_GPIO2_BASE 0xfffbc800
+#define OMAP7XX_GPIO3_BASE 0xfffbd000
+#define OMAP7XX_GPIO4_BASE 0xfffbd800
+#define OMAP7XX_GPIO5_BASE 0xfffbe000
+#define OMAP7XX_GPIO6_BASE 0xfffbe800
+#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
+
+/* mpu gpio */
+static struct __initdata resource omap7xx_mpu_gpio_resources[] = {
+ {
+ .start = OMAP1_MPUIO_VBASE,
+ .end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_7XX_MPUIO,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
+ .virtual_irq_start = IH_MPUIO_BASE,
+ .bank_type = METHOD_MPUIO,
+ .bank_width = 32,
+ .bank_stride = 2,
+};
+
+static struct __initdata platform_device omap7xx_mpu_gpio = {
+ .name = "omap_gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &omap7xx_mpu_gpio_config,
+ },
+ .num_resources = ARRAY_SIZE(omap7xx_mpu_gpio_resources),
+ .resource = omap7xx_mpu_gpio_resources,
+};
+
+/* gpio1 */
+static struct __initdata resource omap7xx_gpio1_resources[] = {
+ {
+ .start = OMAP7XX_GPIO1_BASE,
+ .end = OMAP7XX_GPIO1_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_7XX_GPIO_BANK1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
+ .virtual_irq_start = IH_GPIO_BASE,
+ .bank_type = METHOD_GPIO_7XX,
+ .bank_width = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio1 = {
+ .name = "omap_gpio",
+ .id = 1,
+ .dev = {
+ .platform_data = &omap7xx_gpio1_config,
+ },
+ .num_resources = ARRAY_SIZE(omap7xx_gpio1_resources),
+ .resource = omap7xx_gpio1_resources,
+};
+
+/* gpio2 */
+static struct __initdata resource omap7xx_gpio2_resources[] = {
+ {
+ .start = OMAP7XX_GPIO2_BASE,
+ .end = OMAP7XX_GPIO2_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_7XX_GPIO_BANK2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
+ .virtual_irq_start = IH_GPIO_BASE + 32,
+ .bank_type = METHOD_GPIO_7XX,
+ .bank_width = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio2 = {
+ .name = "omap_gpio",
+ .id = 2,
+ .dev = {
+ .platform_data = &omap7xx_gpio2_config,
+ },
+ .num_resources = ARRAY_SIZE(omap7xx_gpio2_resources),
+ .resource = omap7xx_gpio2_resources,
+};
+
+/* gpio3 */
+static struct __initdata resource omap7xx_gpio3_resources[] = {
+ {
+ .start = OMAP7XX_GPIO3_BASE,
+ .end = OMAP7XX_GPIO3_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_7XX_GPIO_BANK3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
+ .virtual_irq_start = IH_GPIO_BASE + 64,
+ .bank_type = METHOD_GPIO_7XX,
+ .bank_width = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio3 = {
+ .name = "omap_gpio",
+ .id = 3,
+ .dev = {
+ .platform_data = &omap7xx_gpio3_config,
+ },
+ .num_resources = ARRAY_SIZE(omap7xx_gpio3_resources),
+ .resource = omap7xx_gpio3_resources,
+};
+
+/* gpio4 */
+static struct __initdata resource omap7xx_gpio4_resources[] = {
+ {
+ .start = OMAP7XX_GPIO4_BASE,
+ .end = OMAP7XX_GPIO4_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_7XX_GPIO_BANK4,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
+ .virtual_irq_start = IH_GPIO_BASE + 96,
+ .bank_type = METHOD_GPIO_7XX,
+ .bank_width = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio4 = {
+ .name = "omap_gpio",
+ .id = 4,
+ .dev = {
+ .platform_data = &omap7xx_gpio4_config,
+ },
+ .num_resources = ARRAY_SIZE(omap7xx_gpio4_resources),
+ .resource = omap7xx_gpio4_resources,
+};
+
+/* gpio5 */
+static struct __initdata resource omap7xx_gpio5_resources[] = {
+ {
+ .start = OMAP7XX_GPIO5_BASE,
+ .end = OMAP7XX_GPIO5_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_7XX_GPIO_BANK5,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
+ .virtual_irq_start = IH_GPIO_BASE + 128,
+ .bank_type = METHOD_GPIO_7XX,
+ .bank_width = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio5 = {
+ .name = "omap_gpio",
+ .id = 5,
+ .dev = {
+ .platform_data = &omap7xx_gpio5_config,
+ },
+ .num_resources = ARRAY_SIZE(omap7xx_gpio5_resources),
+ .resource = omap7xx_gpio5_resources,
+};
+
+/* gpio6 */
+static struct __initdata resource omap7xx_gpio6_resources[] = {
+ {
+ .start = OMAP7XX_GPIO6_BASE,
+ .end = OMAP7XX_GPIO6_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_7XX_GPIO_BANK6,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
+ .virtual_irq_start = IH_GPIO_BASE + 160,
+ .bank_type = METHOD_GPIO_7XX,
+ .bank_width = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio6 = {
+ .name = "omap_gpio",
+ .id = 6,
+ .dev = {
+ .platform_data = &omap7xx_gpio6_config,
+ },
+ .num_resources = ARRAY_SIZE(omap7xx_gpio6_resources),
+ .resource = omap7xx_gpio6_resources,
+};
+
+static struct __initdata platform_device * omap7xx_gpio_dev[] = {
+ &omap7xx_mpu_gpio,
+ &omap7xx_gpio1,
+ &omap7xx_gpio2,
+ &omap7xx_gpio3,
+ &omap7xx_gpio4,
+ &omap7xx_gpio5,
+ &omap7xx_gpio6,
+};
+
+/*
+ * omap7xx_gpio_init needs to be done before
+ * machine_init functions access gpio APIs.
+ * Hence omap7xx_gpio_init is a postcore_initcall.
+ */
+static int __init omap7xx_gpio_init(void)
+{
+ int i;
+
+ if (!cpu_is_omap7xx())
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
+ platform_device_register(omap7xx_gpio_dev[i]);
+
+ gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev);
+
+ return 0;
+}
+postcore_initcall(omap7xx_gpio_init);
#include <mach/irqs.h>
#include <asm/hardware/gic.h>
-#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \
- (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
-#error "FIXME: OMAP7XX doesn't support multiple-OMAP"
-#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-#define INT_IH2_IRQ INT_7XX_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP15XX)
-#define INT_IH2_IRQ INT_1510_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP16XX)
-#define INT_IH2_IRQ INT_1610_IH2_IRQ
-#else
-#warning "IH2 IRQ defaulted"
-#define INT_IH2_IRQ INT_1510_IH2_IRQ
+/*
+ * We use __glue to avoid errors with multiple definitions of
+ * .globl omap_irq_flags as it's included from entry-armv.S but not
+ * from entry-common.S.
+ */
+#ifdef __glue
+ .pushsection .data
+ .globl omap_irq_flags
+omap_irq_flags:
+ .word 0
+ .popsection
#endif
.macro disable_fiq
beq 1510f
ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
+ ldr \tmp, =omap_irq_flags @ irq flags address
+ ldr \tmp, [\tmp, #0] @ irq flags value
cmp \irqnr, #0
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
- cmpeq \irqnr, #INT_IH2_IRQ
+ cmpeq \irqnr, \tmp
ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
addeqs \irqnr, \irqnr, #32
omap1_mux_init();
}
+/*
+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
+ */
+
+u8 omap_readb(u32 pa)
+{
+ return __raw_readb(OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readb);
+
+u16 omap_readw(u32 pa)
+{
+ return __raw_readw(OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readw);
+
+u32 omap_readl(u32 pa)
+{
+ return __raw_readl(OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readl);
+
+void omap_writeb(u8 v, u32 pa)
+{
+ __raw_writeb(v, OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writeb);
+
+void omap_writew(u16 v, u32 pa)
+{
+ __raw_writew(v, OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writew);
+
+void omap_writel(u32 v, u32 pa)
+{
+ __raw_writel(v, OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writel);
void __init omap_init_irq(void)
{
+ extern unsigned int omap_irq_flags;
int i, j;
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
if (cpu_is_omap7xx()) {
+ omap_irq_flags = INT_7XX_IH2_IRQ;
irq_banks = omap7xx_irq_banks;
irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
+ omap_irq_flags = INT_1510_IH2_IRQ;
irq_banks = omap1510_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
}
if (cpu_is_omap310()) {
+ omap_irq_flags = INT_1510_IH2_IRQ;
irq_banks = omap310_irq_banks;
irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
}
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
if (cpu_is_omap16xx()) {
+ omap_irq_flags = INT_1510_IH2_IRQ;
irq_banks = omap1610_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
}
{
int r;
+ if (!cpu_class_is_omap1())
+ return -ENODEV;
+
if (cpu_is_omap16xx()) {
u16 w;
static int __init
omap_leds_init(void)
{
+ if (!cpu_class_is_omap1())
+ return -ENODEV;
+
if (machine_is_omap_innovator())
leds_event = innovator_leds_event;
},
};
-struct omap_mbox mbox_dsp_info = {
+static struct omap_mbox mbox_dsp_info = {
.name = "dsp",
.ops = &omap1_mbox_ops,
.priv = &omap1_mbox_dsp_priv,
};
-struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
+static struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
static int __devinit omap1_mbox_probe(struct platform_device *pdev)
{
struct resource *mem;
int ret;
- int i;
struct omap_mbox **list;
list = omap1_mboxes;
#define OMAP16XX_MCBSP_REG_NUM 0
#endif
-int __init omap1_mcbsp_init(void)
+static int __init omap1_mcbsp_init(void)
{
+ if (!cpu_class_is_omap1())
+ return -ENODEV;
+
if (cpu_is_omap7xx()) {
omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16);
#define OMAP1XXX_PINS_SZ 0
#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
-int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
+static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
{
static DEFINE_SPINLOCK(mux_spin_lock);
unsigned long flags;
int error;
#endif
+ if (!cpu_class_is_omap1())
+ return -ENODEV;
+
printk("Power Management for TI OMAP.\n");
/*
static int omap1_pm_runtime_resume(struct device *dev)
{
- int ret = 0;
struct clk *iclk, *fclk;
dev_dbg(dev, "%s\n", __func__);
const struct dev_pm_ops *pm;
struct dev_pm_ops *omap_pm;
+ if (!cpu_class_is_omap1())
+ return -ENODEV;
+
pm = platform_bus_get_pm_ops();
if (!pm) {
pr_err("%s: unable to get dev_pm_ops from platform_bus\n",
#include <mach/gpio.h>
#include <plat/fpga.h>
+#include "pm.h"
+
static struct clk * uart1_ck;
static struct clk * uart2_ck;
static struct clk * uart3_ck;
*/
static void __init omap_serial_reset(struct plat_serial8250_port *p)
{
- omap_serial_outp(p, UART_OMAP_MDR1, 0x07); /* disable UART */
+ omap_serial_outp(p, UART_OMAP_MDR1,
+ UART_OMAP_MDR1_DISABLE); /* disable UART */
omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */
- omap_serial_outp(p, UART_OMAP_MDR1, 0x00); /* enable UART */
+ omap_serial_outp(p, UART_OMAP_MDR1,
+ UART_OMAP_MDR1_16X_MODE); /* enable UART */
if (!cpu_is_omap15xx()) {
omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
static int __init omap_init(void)
{
+ if (!cpu_class_is_omap1())
+ return -ENODEV;
+
return platform_device_register(&serial_device);
}
arch_initcall(omap_init);
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
+#include <plat/common.h>
#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
#define OMAP_MPU_TIMER_OFFSET 0x100
select SERIAL_OMAP_CONSOLE
select I2C
select I2C_OMAP
- select MFD
+ select MFD_SUPPORT
select MENELAUS if ARCH_OMAP2
select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
config OMAP_PACKAGE_CBP
bool
+config OMAP_PACKAGE_CBL
+ bool
+
+config OMAP_PACKAGE_CBS
+ bool
+
comment "OMAP Board Type"
depends on ARCH_OMAP2PLUS
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CUS
- select OMAP_MUX
config MACH_OMAP_LDP
bool "OMAP3 LDP board"
default y
select OMAP_PACKAGE_CBB
+config MACH_CRANEBOARD
+ bool "AM3517/05 CRANE board"
+ depends on ARCH_OMAP3
+ select OMAP_PACKAGE_CBB
+
config MACH_OMAP3_PANDORA
bool "OMAP3 Pandora"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
+ select REGULATOR_FIXED_VOLTAGE
config MACH_OMAP3_TOUCHBOOK
bool "OMAP3 Touch Book"
select MACH_NOKIA_N810
select MACH_NOKIA_N810_WIMAX
+config MACH_NOKIA_RM680
+ bool "Nokia RM-680 board"
+ depends on ARCH_OMAP3
+ default y
+ select OMAP_PACKAGE_CBB
+
config MACH_NOKIA_RX51
bool "Nokia RX-51 board"
depends on ARCH_OMAP3
select SERIAL_8250
select SERIAL_CORE_CONSOLE
select SERIAL_8250_CONSOLE
+ select REGULATOR_FIXED_VOLTAGE
config MACH_OMAP_ZOOM3
bool "OMAP3630 Zoom3 board"
select SERIAL_8250
select SERIAL_CORE_CONSOLE
select SERIAL_8250_CONSOLE
+ select REGULATOR_FIXED_VOLTAGE
config MACH_CM_T35
bool "CompuLab CM-T35 module"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CUS
- select OMAP_MUX
config MACH_CM_T3517
bool "CompuLab CM-T3517 module"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
- select OMAP_MUX
config MACH_IGEP0020
bool "IGEP v2 board"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CUS
- select OMAP_MUX
config MACH_OMAP_3630SDP
bool "OMAP3630 SDP board"
bool "OMAP 4430 SDP board"
default y
depends on ARCH_OMAP4
+ select OMAP_PACKAGE_CBL
+ select OMAP_PACKAGE_CBS
config MACH_OMAP4_PANDA
bool "OMAP4 Panda Board"
default y
depends on ARCH_OMAP4
+ select OMAP_PACKAGE_CBL
+ select OMAP_PACKAGE_CBS
config OMAP3_EMU
bool "OMAP3 debugging peripherals"
# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
- common.o
+ common.o gpio.o
omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o
hwmod-common = omap_hwmod.o \
obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o
-AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a
-AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a
+plus_sec := $(call as-instr,.arch_extension sec,+sec)
+AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a$(plus_sec)
# Functions loaded to SRAM
obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o
obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
+obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
# SMS/SDRC
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
hsmmc.o \
board-flash.o
obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
+obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o \
+ sdram-nokia.o \
+ hsmmc.o
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \
- board-rx51-sdram.o \
+ sdram-nokia.o \
board-rx51-peripherals.o \
board-rx51-video.o \
hsmmc.o
-obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \
+obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o \
board-zoom-peripherals.o \
board-flash.o \
hsmmc.o \
board-zoom-debugboard.o
-obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \
+obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o \
board-zoom-peripherals.o \
board-flash.o \
hsmmc.o \
obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
+obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
+
obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \
hsmmc.o
# Platform specific device init code
#endif
-static struct omap_board_config_kernel sdp2430_config[] = {
+static struct omap_board_config_kernel sdp2430_config[] __initdata = {
{OMAP_TAG_LCD, &sdp2430_lcd_config},
};
omap_board_config_size = ARRAY_SIZE(sdp2430_config);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
- omap_gpio_init();
}
static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static void __init omap_2430sdp_init(void)
omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
omap_init_irq();
- omap_gpio_init();
}
static int sdp3430_batt_table[] = {
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
/*
omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
h8mbx00u0mer0em_sdrc_params);
omap_init_irq();
- omap_gpio_init();
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
/*
#include <linux/gpio_keys.h>
#include <linux/regulator/machine.h>
#include <linux/leds.h>
+#include <linux/leds_pwm.h>
#include <mach/hardware.h>
#include <mach/omap4-common.h>
#include <plat/usb.h>
#include <plat/mmc.h>
+#include "mux.h"
#include "hsmmc.h"
#include "timer-gp.h"
#include "control.h"
.num_leds = ARRAY_SIZE(sdp4430_gpio_leds),
};
+static struct led_pwm sdp4430_pwm_leds[] = {
+ {
+ .name = "omap4:green:chrg",
+ .pwm_id = 1,
+ .max_brightness = 255,
+ .pwm_period_ns = 7812500,
+ },
+};
+
+static struct led_pwm_platform_data sdp4430_pwm_data = {
+ .num_leds = ARRAY_SIZE(sdp4430_pwm_leds),
+ .leds = sdp4430_pwm_leds,
+};
+
+static struct platform_device sdp4430_leds_pwm = {
+ .name = "leds_pwm",
+ .id = -1,
+ .dev = {
+ .platform_data = &sdp4430_pwm_data,
+ },
+};
+
static int omap_prox_activate(struct device *dev)
{
gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
&sdp4430_lcd_device,
&sdp4430_gpio_keys_device,
&sdp4430_leds_gpio,
+ &sdp4430_leds_pwm,
};
static struct omap_lcd_config sdp4430_lcd_config __initdata = {
omap2_gp_clockevent_set_gptimer(1);
#endif
gic_init_irq();
- omap_gpio_init();
}
static struct omap_musb_board_data musb_board_data = {
{
I2C_BOARD_INFO("tmp105", 0x48),
},
+ {
+ I2C_BOARD_INFO("bh1780", 0x29),
+ },
};
static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
{
}
}
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux NULL
+#endif
+
static void __init omap_4430sdp_init(void)
{
int status;
+ int package = OMAP_PACKAGE_CBS;
+
+ if (omap_rev() == OMAP4430_REV_ES1_0)
+ package = OMAP_PACKAGE_CBL;
+ omap4_mux_init(board_mux, package);
omap4_i2c_init();
omap_sfh7741prox_init();
--- /dev/null
+/*
+ * Support for AM3517/05 Craneboard
+ * http://www.mistralsolutions.com/products/craneboard.php
+ *
+ * Copyright (C) 2010 Mistral Solutions Pvt Ltd. <www.mistralsolutions.com>
+ * Author: R.Srinath <srinath@mistralsolutions.com>
+ *
+ * Based on mach-omap2/board-am3517evm.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+
+#include "mux.h"
+
+/* Board initialization */
+static struct omap_board_config_kernel am3517_crane_config[] __initdata = {
+};
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux NULL
+#endif
+
+static void __init am3517_crane_init_irq(void)
+{
+ omap_board_config = am3517_crane_config;
+ omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
+
+ omap2_init_common_hw(NULL, NULL);
+ omap_init_irq();
+}
+
+static void __init am3517_crane_init(void)
+{
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ omap_serial_init();
+}
+
+MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
+ .boot_params = 0x80000100,
+ .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+ .init_irq = am3517_crane_init_irq,
+ .init_machine = am3517_crane_init,
+ .timer = &omap_timer,
+MACHINE_END
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
- omap_gpio_init();
}
static struct omap_musb_board_data musb_board_data = {
OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
.ctrl_name = "internal",
};
-static struct omap_board_config_kernel apollon_config[] = {
+static struct omap_board_config_kernel apollon_config[] __initdata = {
{ OMAP_TAG_LCD, &apollon_lcd_config },
};
omap_board_config_size = ARRAY_SIZE(apollon_config);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
- omap_gpio_init();
- apollon_init_smc91x();
}
static void __init apollon_led_init(void)
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static void __init omap_apollon_init(void)
omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
+ apollon_init_smc91x();
apollon_led_init();
apollon_flash_init();
apollon_usb_init();
.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
.phy_reset = true,
- .reset_gpio_port[0] = -EINVAL,
- .reset_gpio_port[1] = -EINVAL,
+ .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6,
+ .reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7,
.reset_gpio_port[2] = -EINVAL
};
cm_t35_vmmc1_supply.dev = mmc[0].dev;
cm_t35_vsim_supply.dev = mmc[0].dev;
- /* setup USB with proper PHY reset GPIOs */
- ehci_pdata.reset_gpio_port[0] = gpio + 6;
- ehci_pdata.reset_gpio_port[1] = gpio + 7;
-
- usb_ehci_init(&ehci_pdata);
-
return 0;
}
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
- omap_gpio_init();
}
static struct omap_board_mux board_mux[] __initdata = {
cm_t35_init_display();
usb_musb_init(&musb_board_data);
+ usb_ehci_init(&ehci_pdata);
}
MACHINE_START(CM_T35, "Compulab CM-T35")
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
- omap_gpio_init();
}
static struct omap_board_mux board_mux[] __initdata = {
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
- omap_gpio_init();
}
static void __init devkit8000_ads7846_init(void)
.hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */
};
-static struct omap_board_config_kernel h4_config[] = {
+static struct omap_board_config_kernel h4_config[] __initdata = {
{ OMAP_TAG_LCD, &h4_lcd_config },
};
omap_board_config_size = ARRAY_SIZE(h4_config);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
- omap_gpio_init();
h4_init_flash();
}
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static void __init omap_h4_init(void)
#include <linux/interrupt.h>
#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
#include <linux/i2c/twl.h>
#include <linux/mmc/host.h>
},
};
-static int igep2_onenand_setup(void __iomem *onenand_base, int freq)
-{
- /* nothing is required to be setup for onenand as of now */
- return 0;
-}
-
static struct omap_onenand_platform_data igep2_onenand_data = {
.parts = igep2_onenand_partitions,
.nr_parts = ARRAY_SIZE(igep2_onenand_partitions),
- .onenand_setup = igep2_onenand_setup,
.dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
};
static void __init igep2_flash_init(void)
{
- u8 cs = 0;
- u8 onenandcs = GPMC_CS_NUM + 1;
+ u8 cs = 0;
+ u8 onenandcs = GPMC_CS_NUM + 1;
- while (cs < GPMC_CS_NUM) {
- u32 ret = 0;
+ for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+ u32 ret;
ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
/* Check if NAND/oneNAND is configured */
if ((ret & 0xC00) == 0x800)
/* NAND found */
- pr_err("IGEP v2: Unsupported NAND found\n");
+ pr_err("IGEP2: Unsupported NAND found\n");
else {
ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
if ((ret & 0x3F) == (ONENAND_MAP >> 24))
/* ONENAND found */
onenandcs = cs;
}
- cs++;
}
+
if (onenandcs > GPMC_CS_NUM) {
- pr_err("IGEP v2: Unable to find configuration in GPMC\n");
+ pr_err("IGEP2: Unable to find configuration in GPMC\n");
return;
}
- if (onenandcs < GPMC_CS_NUM) {
- igep2_onenand_data.cs = onenandcs;
- if (platform_device_register(&igep2_onenand_device) < 0)
- pr_err("IGEP v2: Unable to register OneNAND device\n");
- }
+ igep2_onenand_data.cs = onenandcs;
+
+ if (platform_device_register(&igep2_onenand_device) < 0)
+ pr_err("IGEP2: Unable to register OneNAND device\n");
}
#else
static inline void __init igep2_init_smsc911x(void) { }
#endif
-static struct omap_board_config_kernel igep2_config[] __initdata = {
-};
-
-static struct regulator_consumer_supply igep2_vmmc1_supply = {
- .supply = "vmmc",
-};
+static struct regulator_consumer_supply igep2_vmmc1_supply =
+ REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
static struct regulator_init_data igep2_vmmc1 = {
.consumer_supplies = &igep2_vmmc1_supply,
};
+static struct regulator_consumer_supply igep2_vio_supply =
+ REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
+
+static struct regulator_init_data igep2_vio = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = 1,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &igep2_vio_supply,
+};
+
+static struct regulator_consumer_supply igep2_vmmc2_supply =
+ REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
+
+static struct regulator_init_data igep2_vmmc2 = {
+ .constraints = {
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .always_on = 1,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &igep2_vmmc2_supply,
+};
+
+static struct fixed_voltage_config igep2_vwlan = {
+ .supply_name = "vwlan",
+ .microvolts = 3300000,
+ .gpio = -EINVAL,
+ .enabled_at_boot = 1,
+ .init_data = &igep2_vmmc2,
+};
+
+static struct platform_device igep2_vwlan_device = {
+ .name = "reg-fixed-voltage",
+ .id = 0,
+ .dev = {
+ .platform_data = &igep2_vwlan,
+ },
+};
+
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.name = "gpio-led:green:d1",
.default_trigger = "heartbeat",
.gpio = -EINVAL, /* gets replaced */
+ .active_low = 1,
},
};
static inline void igep2_leds_init(void)
{
if ((gpio_request(IGEP2_GPIO_LED0_RED, "gpio-led:red:d0") == 0) &&
- (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) {
+ (gpio_direction_output(IGEP2_GPIO_LED0_RED, 0) == 0))
gpio_export(IGEP2_GPIO_LED0_RED, 0);
- gpio_set_value(IGEP2_GPIO_LED0_RED, 0);
- } else
+ else
pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n");
if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) &&
- (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) {
+ (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 0) == 0))
gpio_export(IGEP2_GPIO_LED0_GREEN, 0);
- gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0);
- } else
+ else
pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n");
if ((gpio_request(IGEP2_GPIO_LED1_RED, "gpio-led:red:d1") == 0) &&
- (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) {
+ (gpio_direction_output(IGEP2_GPIO_LED1_RED, 0) == 0))
gpio_export(IGEP2_GPIO_LED1_RED, 0);
- gpio_set_value(IGEP2_GPIO_LED1_RED, 0);
- } else
+ else
pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n");
}
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
- /*
- * link regulators to MMC adapters ... we "know" the
- * regulators will be set up only *after* we return.
- */
- igep2_vmmc1_supply.dev = mmc[0].dev;
-
/*
* REVISIT: need ehci-omap hooks for external VBUS
* power switch and overcurrent detect
/* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0)
- && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) {
+ && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0))
gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0);
- gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0);
- } else
+ else
pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n");
#else
igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
static struct platform_device *igep2_devices[] __initdata = {
&igep2_dss_device,
+ &igep2_vwlan_device,
};
static void __init igep2_init_irq(void)
{
- omap_board_config = igep2_config;
- omap_board_config_size = ARRAY_SIZE(igep2_config);
omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
omap_init_irq();
- omap_gpio_init();
}
static struct twl4030_codec_audio_data igep2_audio_data = {
.gpio = &igep2_twl4030_gpio_pdata,
.vmmc1 = &igep2_vmmc1,
.vpll2 = &igep2_vpll2,
-
+ .vio = &igep2_vio,
};
static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = {
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
{
omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
omap_init_irq();
- omap_gpio_init();
}
static struct twl4030_platform_data igep3_twl4030_pdata = {
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static void __init igep3_init(void)
omap_board_config_size = ARRAY_SIZE(ldp_config);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
- omap_gpio_init();
- ldp_init_smsc911x();
}
static struct twl4030_usb_data ldp_usb_data = {
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static struct omap_musb_board_data musb_board_data = {
static void __init omap_ldp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ ldp_init_smsc911x();
omap_i2c_init();
platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
ts_gpio = 54;
},
};
-static struct omap_onenand_platform_data board_onenand_data = {
- .cs = 0,
- .gpio_irq = 26,
- .parts = onenand_partitions,
- .nr_parts = ARRAY_SIZE(onenand_partitions),
- .flags = ONENAND_SYNC_READ,
+static struct omap_onenand_platform_data board_onenand_data[] = {
+ {
+ .cs = 0,
+ .gpio_irq = 26,
+ .parts = onenand_partitions,
+ .nr_parts = ARRAY_SIZE(onenand_partitions),
+ .flags = ONENAND_SYNC_READ,
+ }
};
-
-static void __init n8x0_onenand_init(void)
-{
- gpmc_onenand_init(&board_onenand_data);
-}
-
-#else
-
-static void __init n8x0_onenand_init(void) {}
-
#endif
#if defined(CONFIG_MENELAUS) && \
{
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
- omap_gpio_init();
}
#ifdef CONFIG_OMAP_MUX
OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static void __init n8x0_init_machine(void)
ARRAY_SIZE(n810_i2c_board_info_2));
omap_serial_init();
- n8x0_onenand_init();
+ gpmc_onenand_init(board_onenand_data);
n8x0_mmc_init();
n8x0_usb_init();
}
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
- omap_gpio_init();
}
static struct platform_device *omap3_beagle_devices[] __initdata = {
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static struct omap_musb_board_data musb_board_data = {
omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
omap_init_irq();
- omap_gpio_init();
}
static struct platform_device *omap3_evm_devices[] __initdata = {
OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static struct omap_musb_board_data musb_board_data = {
{
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
- omap_gpio_init();
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static void __init omap3logic_init(void)
},
{
.mmc = 3,
- .caps = MMC_CAP_4_BIT_DATA,
+ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.init_card = pandora_wl1251_init_card,
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
- omap_gpio_init();
}
static void pandora_wl1251_set_power(bool enable)
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static struct omap_musb_board_data musb_board_data = {
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
- omap_gpio_init();
}
static struct platform_device *omap3_stalker_devices[] __initdata = {
OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
{.reg_offset = OMAP_MUX_TERMINATOR},
};
-#else
-#define board_mux NULL
#endif
static struct omap_musb_board_data musb_board_data = {
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static void __init omap3_touchbook_init_irq(void)
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
- omap_gpio_init();
}
static struct platform_device *omap3_touchbook_devices[] __initdata = {
#include "hsmmc.h"
#include "control.h"
+#include "mux.h"
#define GPIO_HUB_POWER 1
#define GPIO_HUB_NRESET 62
{
omap2_init_common_hw(NULL, NULL);
gic_init_irq();
- omap_gpio_init();
}
static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
omap_register_i2c_bus(4, 400, NULL, 0);
return 0;
}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux NULL
+#endif
+
static void __init omap4_panda_init(void)
{
+ int package = OMAP_PACKAGE_CBS;
+
+ if (omap_rev() == OMAP4430_REV_ES1_0)
+ package = OMAP_PACKAGE_CBL;
+ omap4_mux_init(board_mux, package);
+
omap4_panda_i2c_init();
platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
omap_serial_init();
MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
/* Maintainer: David Anders - Texas Instruments Inc */
.boot_params = 0x80000100,
+ .reserve = omap_reserve,
.map_io = omap4_panda_map_io,
.init_irq = omap4_panda_init_irq,
.init_machine = omap4_panda_init,
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
- omap_gpio_init();
}
static struct platform_device *overo_devices[] __initdata = {
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static struct omap_musb_board_data musb_board_data = {
--- /dev/null
+/*
+ * Board support file for Nokia RM-680.
+ *
+ * Copyright (C) 2010 Nokia
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/i2c/twl.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/i2c.h>
+#include <plat/mmc.h>
+#include <plat/usb.h>
+#include <plat/gpmc.h>
+#include <plat/common.h>
+#include <plat/onenand.h>
+
+#include "mux.h"
+#include "hsmmc.h"
+#include "sdram-nokia.h"
+
+static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
+ REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
+};
+
+/* Fixed regulator for internal eMMC */
+static struct regulator_init_data rm680_vemmc = {
+ .constraints = {
+ .name = "rm680_vemmc",
+ .min_uV = 2900000,
+ .max_uV = 2900000,
+ .apply_uV = 1,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS
+ | REGULATOR_CHANGE_MODE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(rm680_vemmc_consumers),
+ .consumer_supplies = rm680_vemmc_consumers,
+};
+
+static struct fixed_voltage_config rm680_vemmc_config = {
+ .supply_name = "VEMMC",
+ .microvolts = 2900000,
+ .gpio = 157,
+ .startup_delay = 150,
+ .enable_high = 1,
+ .init_data = &rm680_vemmc,
+};
+
+static struct platform_device rm680_vemmc_device = {
+ .name = "reg-fixed-voltage",
+ .dev = {
+ .platform_data = &rm680_vemmc_config,
+ },
+};
+
+static struct platform_device *rm680_peripherals_devices[] __initdata = {
+ &rm680_vemmc_device,
+};
+
+/* TWL */
+static struct twl4030_gpio_platform_data rm680_gpio_data = {
+ .gpio_base = OMAP_MAX_GPIO_LINES,
+ .irq_base = TWL4030_GPIO_IRQ_BASE,
+ .irq_end = TWL4030_GPIO_IRQ_END,
+ .pullups = BIT(0),
+ .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15),
+};
+
+static struct twl4030_usb_data rm680_usb_data = {
+ .usb_mode = T2_USB_MODE_ULPI,
+};
+
+static struct twl4030_platform_data rm680_twl_data = {
+ .irq_base = TWL4030_IRQ_BASE,
+ .irq_end = TWL4030_IRQ_END,
+ .gpio = &rm680_gpio_data,
+ .usb = &rm680_usb_data,
+ /* add rest of the children here */
+};
+
+static struct i2c_board_info __initdata rm680_twl_i2c_board_info[] = {
+ {
+ I2C_BOARD_INFO("twl5031", 0x48),
+ .flags = I2C_CLIENT_WAKE,
+ .irq = INT_34XX_SYS_NIRQ,
+ .platform_data = &rm680_twl_data,
+ },
+};
+
+static void __init rm680_i2c_init(void)
+{
+ omap_register_i2c_bus(1, 2900, rm680_twl_i2c_board_info,
+ ARRAY_SIZE(rm680_twl_i2c_board_info));
+ omap_register_i2c_bus(2, 400, NULL, 0);
+ omap_register_i2c_bus(3, 400, NULL, 0);
+}
+
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+ defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+static struct omap_onenand_platform_data board_onenand_data[] = {
+ {
+ .gpio_irq = 65,
+ .flags = ONENAND_SYNC_READWRITE,
+ }
+};
+#endif
+
+/* eMMC */
+static struct omap2_hsmmc_info mmc[] __initdata = {
+ {
+ .name = "internal",
+ .mmc = 2,
+ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED,
+ .gpio_cd = -EINVAL,
+ .gpio_wp = -EINVAL,
+ },
+ { /* Terminator */ }
+};
+
+static void __init rm680_peripherals_init(void)
+{
+ platform_add_devices(rm680_peripherals_devices,
+ ARRAY_SIZE(rm680_peripherals_devices));
+ rm680_i2c_init();
+ gpmc_onenand_init(board_onenand_data);
+ omap2_hsmmc_init(mmc);
+}
+
+static void __init rm680_init_irq(void)
+{
+ struct omap_sdrc_params *sdrc_params;
+
+ sdrc_params = nokia_get_sdram_timings();
+ omap2_init_common_hw(sdrc_params, sdrc_params);
+ omap_init_irq();
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#endif
+
+static struct omap_musb_board_data rm680_musb_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_PERIPHERAL,
+ .power = 100,
+};
+
+static void __init rm680_init(void)
+{
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ omap_serial_init();
+ usb_musb_init(&rm680_musb_data);
+ rm680_peripherals_init();
+}
+
+static void __init rm680_map_io(void)
+{
+ omap2_set_globals_3xxx();
+ omap34xx_map_common_io();
+}
+
+MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
+ .boot_params = 0x80000100,
+ .map_io = rm680_map_io,
+ .reserve = omap_reserve,
+ .init_irq = rm680_init_irq,
+ .init_machine = rm680_init,
+ .timer = &omap_timer,
+MACHINE_END
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/mmc/host.h>
-#include <sound/tlv320aic3x.h>
#include <plat/mcspi.h>
#include <plat/board.h>
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
+static struct omap_mux_partition *partition;
+
/*
* Current flows to eMMC when eMMC is off and the data lines are pulled up,
* so pull them down. N.B. we pull 8 lines because we are using 8 lines.
static void rx51_mmc2_remux(struct device *dev, int slot, int power_on)
{
if (power_on)
- omap_mux_write_array(rx51_mmc2_on_mux);
+ omap_mux_write_array(partition, rx51_mmc2_on_mux);
else
- omap_mux_write_array(rx51_mmc2_off_mux);
+ omap_mux_write_array(partition, rx51_mmc2_off_mux);
}
static struct omap2_hsmmc_info mmc[] __initdata = {
/* tlv320aic3x analog supplies */
REGULATOR_SUPPLY("AVDD", "2-0018"),
REGULATOR_SUPPLY("DRVDD", "2-0018"),
+ REGULATOR_SUPPLY("AVDD", "2-0019"),
+ REGULATOR_SUPPLY("DRVDD", "2-0019"),
/* tpa6130a2 */
REGULATOR_SUPPLY("Vdd", "2-0060"),
/* Keep vmmc as last item. It is not iterated for newer boards */
/* tlv320aic3x digital supplies */
REGULATOR_SUPPLY("IOVDD", "2-0018"),
REGULATOR_SUPPLY("DVDD", "2-0018"),
+ REGULATOR_SUPPLY("IOVDD", "2-0019"),
+ REGULATOR_SUPPLY("DVDD", "2-0019"),
};
#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
.vio = &rx51_vio,
};
-static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = {
+static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata_or_module = {
.id = TPA6130A2,
.power_gpio = 98,
};
.gpio_reset = 60,
};
+static struct aic3x_pdata rx51_aic3x_data2 = {
+ .gpio_reset = 60,
+};
+
static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
{
I2C_BOARD_INFO("tlv320aic3x", 0x18),
.platform_data = &rx51_aic3x_data,
},
+ {
+ I2C_BOARD_INFO("tlv320aic3x", 0x19),
+ .platform_data = &rx51_aic3x_data2,
+ },
#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
{
I2C_BOARD_INFO("tsl2563", 0x29),
},
};
-static struct omap_onenand_platform_data board_onenand_data = {
- .cs = 0,
- .gpio_irq = 65,
- .parts = onenand_partitions,
- .nr_parts = ARRAY_SIZE(onenand_partitions),
- .flags = ONENAND_SYNC_READWRITE,
+static struct omap_onenand_platform_data board_onenand_data[] = {
+ {
+ .cs = 0,
+ .gpio_irq = 65,
+ .parts = onenand_partitions,
+ .nr_parts = ARRAY_SIZE(onenand_partitions),
+ .flags = ONENAND_SYNC_READWRITE,
+ }
};
-
-static void __init board_onenand_init(void)
-{
- gpmc_onenand_init(&board_onenand_data);
-}
-
-#else
-
-static inline void board_onenand_init(void)
-{
-}
-
#endif
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
void __init rx51_peripherals_init(void)
{
rx51_i2c_init();
- board_onenand_init();
+ gpmc_onenand_init(board_onenand_data);
board_smc91x_init();
rx51_add_gpio_keys();
rx51_init_wl1251();
spi_register_board_info(rx51_peripherals_spi_board_info,
ARRAY_SIZE(rx51_peripherals_spi_board_info));
- omap2_hsmmc_init(mmc);
+
+ partition = omap_mux_get("core");
+ if (partition)
+ omap2_hsmmc_init(mmc);
+
platform_device_register(&rx51_charger_device);
}
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/mm.h>
-
#include <asm/mach-types.h>
#include <plat/display.h>
#include <plat/vram.h>
#include "mux.h"
#define RX51_LCD_RESET_GPIO 90
+/* REVISIT to verify with rx51.c at sound/soc/omap */
+#define RX51_TVOUT_SEL_GPIO 40
+
#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
gpio_set_value(dssdev->reset_gpio, 0);
}
+static int rx51_tvout_enable(struct omap_dss_device *dssdev)
+{
+ gpio_set_value(dssdev->reset_gpio, 1);
+ return 0;
+}
+
+static void rx51_tvout_disable(struct omap_dss_device *dssdev)
+{
+ gpio_set_value(dssdev->reset_gpio, 0);
+}
+
static struct omap_dss_device rx51_lcd_device = {
.name = "lcd",
.driver_name = "panel-acx565akm",
.platform_disable = rx51_lcd_disable,
};
+static struct omap_dss_device rx51_tv_device = {
+ .name = "tv",
+ .type = OMAP_DISPLAY_TYPE_VENC,
+ .driver_name = "venc",
+ .phy.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE,
+ .reset_gpio = RX51_TVOUT_SEL_GPIO,
+ .platform_enable = rx51_tvout_enable,
+ .platform_disable = rx51_tvout_disable,
+};
+
static struct omap_dss_device *rx51_dss_devices[] = {
&rx51_lcd_device,
+ &rx51_tv_device,
};
static struct omap_dss_board_info rx51_dss_board_info = {
gpio_direction_output(RX51_LCD_RESET_GPIO, 1);
+ /* REVISIT to verify with rx51.c at sound/soc/omap */
+ gpio_direction_output(RX51_TVOUT_SEL_GPIO, 1);
+
platform_add_devices(rx51_video_devices,
ARRAY_SIZE(rx51_video_devices));
return 0;
#include "mux.h"
#include "pm.h"
+#include "sdram-nokia.h"
#define RX51_GPIO_SLEEP_IND 162
-struct omap_sdrc_params *rx51_get_sdram_timings(void);
extern void rx51_video_mem_init(void);
static struct gpio_led gpio_leds[] = {
omap_board_config = rx51_config;
omap_board_config_size = ARRAY_SIZE(rx51_config);
omap3_pm_init_cpuidle(rx51_cpuidle_params);
- sdrc_params = rx51_get_sdram_timings();
+ sdrc_params = nokia_get_sdram_timings();
omap2_init_common_hw(sdrc_params, sdrc_params);
omap_init_irq();
- omap_gpio_init();
}
extern void __init rx51_peripherals_init(void);
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-#else
-#define board_mux NULL
#endif
static struct omap_musb_board_data musb_board_data = {
.board_ref_clock = 1,
};
-static struct omap2_hsmmc_info mmc[] __initdata = {
+static struct omap2_hsmmc_info mmc[] = {
{
.name = "external",
.mmc = 1,
/*
- * Copyright (C) 2009 Texas Instruments Inc.
+ * Copyright (C) 2009-2010 Texas Instruments Inc.
+ * Mikkel Christensen <mlc@ti.com>
+ * Felipe Balbi <balbi@ti.com>
*
+ * Modified from mach-omap2/board-ldp.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/gpio.h>
+#include <linux/i2c/twl.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-#include <mach/board-zoom.h>
-
#include <plat/common.h>
#include <plat/board.h>
#include <plat/usb.h>
+#include <mach/board-zoom.h>
+
#include "board-flash.h"
#include "mux.h"
+#include "sdram-micron-mt46h32m32lf-6.h"
#include "sdram-hynix-h8mbx00u0mer-0em.h"
-static struct omap_board_config_kernel zoom_config[] __initdata = {
+#define ZOOM3_EHCI_RESET_GPIO 64
+
+static void __init omap_zoom_init_irq(void)
+{
+ if (machine_is_omap_zoom2())
+ omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+ mt46h32m32lf6_sdrc_params);
+ else if (machine_is_omap_zoom3())
+ omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
+ h8mbx00u0mer0em_sdrc_params);
+
+ omap_init_irq();
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+ /* WLAN IRQ - GPIO 162 */
+ OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
+ /* WLAN POWER ENABLE - GPIO 101 */
+ OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+ /* WLAN SDIO: MMC3 CMD */
+ OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
+ /* WLAN SDIO: MMC3 CLK */
+ OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+ /* WLAN SDIO: MMC3 DAT[0-3] */
+ OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+ OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+ OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+ OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
};
+#endif
static struct mtd_partition zoom_nand_partitions[] = {
/* All the partition sizes are listed in terms of NAND block size */
},
};
-static void __init omap_zoom_init_irq(void)
-{
- omap_board_config = zoom_config;
- omap_board_config_size = ARRAY_SIZE(zoom_config);
- omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
- h8mbx00u0mer0em_sdrc_params);
- omap_init_irq();
- omap_gpio_init();
-}
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
- /* WLAN IRQ - GPIO 162 */
- OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
- /* WLAN POWER ENABLE - GPIO 101 */
- OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
- /* WLAN SDIO: MMC3 CMD */
- OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
- /* WLAN SDIO: MMC3 CLK */
- OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
- /* WLAN SDIO: MMC3 DAT[0-3] */
- OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
- OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
- OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
- OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
- { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define board_mux NULL
-#endif
-
static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
.phy_reset = true,
.reset_gpio_port[0] = -EINVAL,
- .reset_gpio_port[1] = 64,
+ .reset_gpio_port[1] = ZOOM3_EHCI_RESET_GPIO,
.reset_gpio_port[2] = -EINVAL,
};
static void __init omap_zoom_init(void)
{
- omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
- zoom_peripherals_init();
+ if (machine_is_omap_zoom2()) {
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ } else if (machine_is_omap_zoom3()) {
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
+ omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT);
+ usb_ehci_init(&ehci_pdata);
+ }
+
board_nand_init(zoom_nand_partitions,
- ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
+ ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
zoom_debugboard_init();
-
- omap_mux_init_gpio(64, OMAP_PIN_OUTPUT);
- usb_ehci_init(&ehci_pdata);
+ zoom_peripherals_init();
}
+MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
+ .boot_params = 0x80000100,
+ .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+ .init_irq = omap_zoom_init_irq,
+ .init_machine = omap_zoom_init,
+ .timer = &omap_timer,
+MACHINE_END
+
MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
+++ /dev/null
-/*
- * Copyright (C) 2009 Texas Instruments Inc.
- * Mikkel Christensen <mlc@ti.com>
- *
- * Modified from mach-omap2/board-ldp.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/gpio.h>
-#include <linux/i2c/twl.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <plat/common.h>
-#include <plat/board.h>
-
-#include <mach/board-zoom.h>
-
-#include "board-flash.h"
-#include "mux.h"
-#include "sdram-micron-mt46h32m32lf-6.h"
-
-static void __init omap_zoom2_init_irq(void)
-{
- omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
- mt46h32m32lf6_sdrc_params);
- omap_init_irq();
- omap_gpio_init();
-}
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
- /* WLAN IRQ - GPIO 162 */
- OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
- /* WLAN POWER ENABLE - GPIO 101 */
- OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
- /* WLAN SDIO: MMC3 CMD */
- OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
- /* WLAN SDIO: MMC3 CLK */
- OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
- /* WLAN SDIO: MMC3 DAT[0-3] */
- OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
- OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
- OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
- OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
- { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define board_mux NULL
-#endif
-
-static struct mtd_partition zoom_nand_partitions[] = {
- /* All the partition sizes are listed in terms of NAND block size */
- {
- .name = "X-Loader-NAND",
- .offset = 0,
- .size = 4 * (64 * 2048), /* 512KB, 0x80000 */
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "U-Boot-NAND",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
- .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "Boot Env-NAND",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
- .size = 2 * (64 * 2048), /* 256KB, 0x40000 */
- },
- {
- .name = "Kernel-NAND",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/
- .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */
- },
- {
- .name = "system",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */
- .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */
- },
- {
- .name = "userdata",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/
- .size = 256 * (64 * 2048), /* 32M, 0x2000000 */
- },
- {
- .name = "cache",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/
- .size = 256 * (64 * 2048), /* 32M, 0x2000000 */
- },
-};
-
-static void __init omap_zoom2_init(void)
-{
- omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
- zoom_peripherals_init();
- board_nand_init(zoom_nand_partitions,
- ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
- zoom_debugboard_init();
-}
-
-MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
- .boot_params = 0x80000100,
- .map_io = omap3_map_io,
- .reserve = omap_reserve,
- .init_irq = omap_zoom2_init_irq,
- .init_machine = omap_zoom2_init,
- .timer = &omap_timer,
-MACHINE_END
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X),
- CLK("i2c_omap.1", "ick", &i2c1_ick, CK_242X),
- CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
- CLK("i2c_omap.2", "ick", &i2c2_ick, CK_242X),
- CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
+ CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
+ CLK("omap_i2c.1", "fck", &i2c1_fck, CK_242X),
+ CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
+ CLK("omap_i2c.2", "fck", &i2c2_fck, CK_242X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
CLK(NULL, "fac_fck", &fac_fck, CK_243X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
- CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X),
- CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
- CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X),
- CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
+ CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
+ CLK("omap_i2c.1", "fck", &i2chs1_fck, CK_243X),
+ CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
+ CLK("omap_i2c.2", "fck", &i2chs2_fck, CK_243X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
- CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX),
- CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX),
- CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX),
+ CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
+ CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
+ CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX),
CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
- CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX),
- CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX),
- CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX),
+ CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
+ CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
+ CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
- CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X),
- CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X),
- CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
- CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
+ CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X),
+ CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X),
+ CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X),
+ CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X),
CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
CLK(NULL, "iss_fck", &iss_fck, CK_443X),
CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
- CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X),
- CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X),
- CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X),
- CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X),
+ CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
+ CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
+ CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
+ CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
#define OMAP24XX_ST_HDQ_MASK (1 << 23)
#define OMAP2420_ST_I2C2_SHIFT 20
#define OMAP2420_ST_I2C2_MASK (1 << 20)
+#define OMAP2430_ST_I2CHS1_SHIFT 19
+#define OMAP2430_ST_I2CHS1_MASK (1 << 19)
#define OMAP2420_ST_I2C1_SHIFT 19
#define OMAP2420_ST_I2C1_MASK (1 << 19)
+#define OMAP2430_ST_I2CHS2_SHIFT 20
+#define OMAP2430_ST_I2CHS2_MASK (1 << 20)
#define OMAP24XX_ST_MCBSP2_SHIFT 16
#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
#define OMAP24XX_ST_MCBSP1_SHIFT 15
static void __init omap_hsmmc_reset(void)
{
u32 i, nr_controllers;
+ struct clk *iclk, *fclk;
if (cpu_is_omap242x())
return;
for (i = 0; i < nr_controllers; i++) {
u32 v, base = 0;
- struct clk *iclk, *fclk;
struct device *dev = &dummy_pdev.dev;
switch (i) {
dummy_pdev.id = i;
dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
iclk = clk_get(dev, "ick");
- if (iclk && clk_enable(iclk))
- iclk = NULL;
+ if (IS_ERR(iclk))
+ goto err1;
+ if (clk_enable(iclk))
+ goto err2;
fclk = clk_get(dev, "fck");
- if (fclk && clk_enable(fclk))
- fclk = NULL;
-
- if (!iclk || !fclk) {
- printk(KERN_WARNING
- "%s: Unable to enable clocks for MMC%d, "
- "cannot reset.\n", __func__, i);
- break;
- }
+ if (IS_ERR(fclk))
+ goto err3;
+ if (clk_enable(fclk))
+ goto err4;
omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
v = omap_readl(base + MMCHS_SYSSTATUS);
MMCHS_SYSSTATUS_RESETDONE))
cpu_relax();
- if (fclk) {
- clk_disable(fclk);
- clk_put(fclk);
- }
- if (iclk) {
- clk_disable(iclk);
- clk_put(iclk);
- }
+ clk_disable(fclk);
+ clk_put(fclk);
+ clk_disable(iclk);
+ clk_put(iclk);
}
+ return;
+
+err4:
+ clk_put(fclk);
+err3:
+ clk_disable(iclk);
+err2:
+ clk_put(iclk);
+err1:
+ printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
+ "cannot reset.\n", __func__, i);
}
#else
static inline void omap_hsmmc_reset(void) {}
--- /dev/null
+/*
+ * OMAP2+ specific gpio initialization
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author:
+ * Charulatha V <charu@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+
+static struct omap_device_pm_latency omap_gpio_latency[] = {
+ [0] = {
+ .deactivate_func = omap_device_idle_hwmods,
+ .activate_func = omap_device_enable_hwmods,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+ },
+};
+
+static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
+{
+ struct omap_device *od;
+ struct omap_gpio_platform_data *pdata;
+ struct omap_gpio_dev_attr *dev_attr;
+ char *name = "omap_gpio";
+ int id;
+
+ /*
+ * extract the device id from name field available in the
+ * hwmod database and use the same for constructing ids for
+ * gpio devices.
+ * CAUTION: Make sure the name in the hwmod database does
+ * not change. If changed, make corresponding change here
+ * or make use of static variable mechanism to handle this.
+ */
+ sscanf(oh->name, "gpio%d", &id);
+
+ pdata = kzalloc(sizeof(struct omap_gpio_platform_data), GFP_KERNEL);
+ if (!pdata) {
+ pr_err("gpio%d: Memory allocation failed\n", id);
+ return -ENOMEM;
+ }
+
+ dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr;
+ pdata->bank_width = dev_attr->bank_width;
+ pdata->dbck_flag = dev_attr->dbck_flag;
+ pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
+
+ switch (oh->class->rev) {
+ case 0:
+ case 1:
+ pdata->bank_type = METHOD_GPIO_24XX;
+ break;
+ case 2:
+ pdata->bank_type = METHOD_GPIO_44XX;
+ break;
+ default:
+ WARN(1, "Invalid gpio bank_type\n");
+ kfree(pdata);
+ return -EINVAL;
+ }
+
+ od = omap_device_build(name, id - 1, oh, pdata,
+ sizeof(*pdata), omap_gpio_latency,
+ ARRAY_SIZE(omap_gpio_latency),
+ false);
+ kfree(pdata);
+
+ if (IS_ERR(od)) {
+ WARN(1, "Cant build omap_device for %s:%s.\n",
+ name, oh->name);
+ return PTR_ERR(od);
+ }
+
+ gpio_bank_count++;
+ return 0;
+}
+
+/*
+ * gpio_init needs to be done before
+ * machine_init functions access gpio APIs.
+ * Hence gpio_init is a postcore_initcall.
+ */
+static int __init omap2_gpio_init(void)
+{
+ return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init,
+ NULL);
+}
+postcore_initcall(omap2_gpio_init);
*/
#ifdef MULTI_OMAP2
+
+/*
+ * We use __glue to avoid errors with multiple definitions of
+ * .globl omap_irq_base as it's included from entry-armv.S but not
+ * from entry-common.S.
+ */
+#ifdef __glue
.pushsection .data
-omap_irq_base: .word 0
+ .globl omap_irq_base
+omap_irq_base:
+ .word 0
.popsection
+#endif
- /* Configure the interrupt base on the first interrupt */
+ /*
+ * Configure the interrupt base on the first interrupt.
+ * See also omap_irq_base_init for setting omap_irq_base.
+ */
.macro get_irqnr_preamble, base, tmp
-9:
ldr \base, =omap_irq_base @ irq base address
ldr \base, [\base, #0] @ irq base value
- cmp \base, #0 @ already configured?
- bne 9997f @ nothing to do
-
- mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
- and \tmp, \tmp, #0x000f0000 @ only check architecture
- cmp \tmp, #0x00070000 @ is v6?
- beq 2400f @ found v6 so it's omap24xx
- mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
- and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9
- cmp \tmp, #0x00000080 @ cortex A-8?
- beq 3400f @ found A-8 so it's omap34xx
- cmp \tmp, #0x00000090 @ cortex A-9?
- beq 4400f @ found A-9 so it's omap44xx
-2400: ldr \base, =OMAP2_IRQ_BASE
- ldr \tmp, =omap_irq_base
- str \base, [\tmp, #0]
- b 9b
-3400: ldr \base, =OMAP3_IRQ_BASE
- ldr \tmp, =omap_irq_base
- str \base, [\tmp, #0]
- b 9b
-4400: ldr \base, =OMAP4_IRQ_BASE
- ldr \tmp, =omap_irq_base
- str \base, [\tmp, #0]
- b 9b
-9997:
.endm
/* Check the pending interrupts. Note that base already set */
#include "clockdomains.h"
#include <plat/omap_hwmod.h>
+#include <plat/multi.h>
/*
* The machine specific code may provide the extra mapping besides the
return v;
}
+/*
+ * Initialize asm_irq_base for entry-macro.S
+ */
+static inline void omap_irq_base_init(void)
+{
+ extern void __iomem *omap_irq_base;
+
+#ifdef MULTI_OMAP2
+ if (cpu_is_omap24xx())
+ omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
+ else if (cpu_is_omap34xx())
+ omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
+ else if (cpu_is_omap44xx())
+ omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
+ else
+ pr_err("Could not initialize omap_irq_base\n");
+#endif
+}
+
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
_omap2_init_reprogram_sdrc();
}
gpmc_init();
+
+ omap_irq_base_init();
+}
+
+/*
+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
+ */
+
+u8 omap_readb(u32 pa)
+{
+ return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readb);
+
+u16 omap_readw(u32 pa)
+{
+ return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readw);
+
+u32 omap_readl(u32 pa)
+{
+ return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readl);
+
+void omap_writeb(u8 v, u32 pa)
+{
+ __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writeb);
+
+void omap_writew(u16 v, u32 pa)
+{
+ __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writew);
+
+void omap_writel(u32 v, u32 pa)
+{
+ __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
}
+EXPORT_SYMBOL(omap_writel);
void omap3_intc_prepare_idle(void)
{
- /* Disable autoidle as it can stall interrupt controller */
+ /*
+ * Disable autoidle as it can stall interrupt controller,
+ * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
+ */
intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
}
/* FIXME: the following structs should be filled automatically by the user id */
-#if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
.tx_fifo = {
};
#endif
-#if defined(CONFIG_ARCH_OMAP3430)
+#if defined(CONFIG_ARCH_OMAP3)
struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
#endif
if (false)
;
-#if defined(CONFIG_ARCH_OMAP3430)
- else if (cpu_is_omap3430()) {
+#if defined(CONFIG_ARCH_OMAP3)
+ else if (cpu_is_omap34xx()) {
list = omap3_mboxes;
list[0]->irq = platform_get_irq_byname(pdev, "dsp");
}
#endif
-#if defined(CONFIG_ARCH_OMAP2420)
- else if (cpu_is_omap2420()) {
+#if defined(CONFIG_ARCH_OMAP2)
+ else if (cpu_is_omap2430()) {
+ list = omap2_mboxes;
+
+ list[0]->irq = platform_get_irq_byname(pdev, "dsp");
+ } else if (cpu_is_omap2420()) {
list = omap2_mboxes;
list[0]->irq = platform_get_irq_byname(pdev, "dsp");
iounmap(mbox_base);
return ret;
}
- return 0;
- return ret;
+ return 0;
}
static int __devexit omap2_mbox_remove(struct platform_device *pdev)
/*
* linux/arch/arm/mach-omap2/mux.c
*
- * OMAP2 and OMAP3 pin multiplexing configurations
+ * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
*
- * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ * Copyright (C) 2004 - 2010 Texas Instruments Inc.
* Copyright (C) 2003 - 2008 Nokia Corporation
*
* Written by Tony Lindgren
#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
#define OMAP_MUX_BASE_SZ 0x5ca
-#define MUXABLE_GPIO_MODE3 BIT(0)
struct omap_mux_entry {
struct omap_mux mux;
struct list_head node;
};
-static unsigned long mux_phys;
-static void __iomem *mux_base;
-static u8 omap_mux_flags;
+static LIST_HEAD(mux_partitions);
+static DEFINE_MUTEX(muxmode_mutex);
-u16 omap_mux_read(u16 reg)
+struct omap_mux_partition *omap_mux_get(const char *name)
{
- if (cpu_is_omap24xx())
- return __raw_readb(mux_base + reg);
+ struct omap_mux_partition *partition;
+
+ list_for_each_entry(partition, &mux_partitions, node) {
+ if (!strcmp(name, partition->name))
+ return partition;
+ }
+
+ return NULL;
+}
+
+u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
+{
+ if (partition->flags & OMAP_MUX_REG_8BIT)
+ return __raw_readb(partition->base + reg);
else
- return __raw_readw(mux_base + reg);
+ return __raw_readw(partition->base + reg);
}
-void omap_mux_write(u16 val, u16 reg)
+void omap_mux_write(struct omap_mux_partition *partition, u16 val,
+ u16 reg)
{
- if (cpu_is_omap24xx())
- __raw_writeb(val, mux_base + reg);
+ if (partition->flags & OMAP_MUX_REG_8BIT)
+ __raw_writeb(val, partition->base + reg);
else
- __raw_writew(val, mux_base + reg);
+ __raw_writew(val, partition->base + reg);
}
-void omap_mux_write_array(struct omap_board_mux *board_mux)
+void omap_mux_write_array(struct omap_mux_partition *partition,
+ struct omap_board_mux *board_mux)
{
- while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
- omap_mux_write(board_mux->value, board_mux->reg_offset);
+ while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
+ omap_mux_write(partition, board_mux->value,
+ board_mux->reg_offset);
board_mux++;
}
}
-static LIST_HEAD(muxmodes);
-static DEFINE_MUTEX(muxmode_mutex);
-
#ifdef CONFIG_OMAP_MUX
static char *omap_mux_options;
-int __init omap_mux_init_gpio(int gpio, int val)
+static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
+ int gpio, int val)
{
struct omap_mux_entry *e;
struct omap_mux *gpio_mux = NULL;
u16 old_mode;
u16 mux_mode;
int found = 0;
+ struct list_head *muxmodes = &partition->muxmodes;
if (!gpio)
return -EINVAL;
- list_for_each_entry(e, &muxmodes, node) {
+ list_for_each_entry(e, muxmodes, node) {
struct omap_mux *m = &e->mux;
if (gpio == m->gpio) {
gpio_mux = m;
}
if (found == 0) {
- printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
+ pr_err("%s: Could not set gpio%i\n", __func__, gpio);
return -ENODEV;
}
if (found > 1) {
- printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n",
- found, gpio);
+ pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__,
+ found, gpio);
return -EINVAL;
}
- old_mode = omap_mux_read(gpio_mux->reg_offset);
+ old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
- if (omap_mux_flags & MUXABLE_GPIO_MODE3)
+ if (partition->flags & OMAP_MUX_GPIO_IN_MODE3)
mux_mode |= OMAP_MUX_MODE3;
else
mux_mode |= OMAP_MUX_MODE4;
- printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n",
- gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
- omap_mux_write(mux_mode, gpio_mux->reg_offset);
+ pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
+ gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
+ omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
return 0;
}
-int __init omap_mux_init_signal(const char *muxname, int val)
+int __init omap_mux_init_gpio(int gpio, int val)
+{
+ struct omap_mux_partition *partition;
+ int ret;
+
+ list_for_each_entry(partition, &mux_partitions, node) {
+ ret = _omap_mux_init_gpio(partition, gpio, val);
+ if (!ret)
+ return ret;
+ }
+
+ return -ENODEV;
+}
+
+static int __init _omap_mux_init_signal(struct omap_mux_partition *partition,
+ const char *muxname, int val)
{
struct omap_mux_entry *e;
const char *mode_name;
int found = 0, mode0_len = 0;
+ struct list_head *muxmodes = &partition->muxmodes;
mode_name = strchr(muxname, '.');
if (mode_name) {
mode_name = muxname;
}
- list_for_each_entry(e, &muxmodes, node) {
+ list_for_each_entry(e, muxmodes, node) {
struct omap_mux *m = &e->mux;
char *m0_entry = m->muxnames[0];
int i;
u16 old_mode;
u16 mux_mode;
- old_mode = omap_mux_read(m->reg_offset);
+ old_mode = omap_mux_read(partition,
+ m->reg_offset);
mux_mode = val | i;
- printk(KERN_DEBUG "mux: Setting signal "
- "%s.%s 0x%04x -> 0x%04x\n",
- m0_entry, muxname, old_mode, mux_mode);
- omap_mux_write(mux_mode, m->reg_offset);
+ pr_debug("%s: Setting signal "
+ "%s.%s 0x%04x -> 0x%04x\n", __func__,
+ m0_entry, muxname, old_mode, mux_mode);
+ omap_mux_write(partition, mux_mode,
+ m->reg_offset);
found++;
}
}
return 0;
if (found > 1) {
- printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n",
- found, muxname);
+ pr_err("%s: Multiple signal paths (%i) for %s\n", __func__,
+ found, muxname);
return -EINVAL;
}
- printk(KERN_ERR "mux: Could not set signal %s\n", muxname);
+ pr_err("%s: Could not set signal %s\n", __func__, muxname);
return -ENODEV;
}
+int __init omap_mux_init_signal(const char *muxname, int val)
+{
+ struct omap_mux_partition *partition;
+ int ret;
+
+ list_for_each_entry(partition, &mux_partitions, node) {
+ ret = _omap_mux_init_signal(partition, muxname, val);
+ if (!ret)
+ return ret;
+ }
+
+ return -ENODEV;
+
+}
+
#ifdef CONFIG_DEBUG_FS
#define OMAP_MUX_MAX_NR_FLAGS 10
} while (i-- > 0);
}
-#define OMAP_MUX_DEFNAME_LEN 16
+#define OMAP_MUX_DEFNAME_LEN 32
static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
{
+ struct omap_mux_partition *partition = s->private;
struct omap_mux_entry *e;
+ u8 omap_gen = omap_rev() >> 28;
- list_for_each_entry(e, &muxmodes, node) {
+ list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
char m0_def[OMAP_MUX_DEFNAME_LEN];
char *m0_name = m->muxnames[0];
}
m0_def[i] = toupper(m0_name[i]);
}
- val = omap_mux_read(m->reg_offset);
+ val = omap_mux_read(partition, m->reg_offset);
mode = val & OMAP_MUX_MODE7;
-
- seq_printf(s, "OMAP%i_MUX(%s, ",
- cpu_is_omap34xx() ? 3 : 0, m0_def);
+ if (mode != 0)
+ seq_printf(s, "/* %s */\n", m->muxnames[mode]);
+
+ /*
+ * XXX: Might be revisited to support differences accross
+ * same OMAP generation.
+ */
+ seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
omap_mux_decode(s, val);
seq_printf(s, "),\n");
}
static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
{
- return single_open(file, omap_mux_dbg_board_show, &inode->i_private);
+ return single_open(file, omap_mux_dbg_board_show, inode->i_private);
}
static const struct file_operations omap_mux_dbg_board_fops = {
.release = single_release,
};
+static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux)
+{
+ struct omap_mux_partition *partition;
+
+ list_for_each_entry(partition, &mux_partitions, node) {
+ struct list_head *muxmodes = &partition->muxmodes;
+ struct omap_mux_entry *e;
+
+ list_for_each_entry(e, muxmodes, node) {
+ struct omap_mux *m = &e->mux;
+
+ if (m == mux)
+ return partition;
+ }
+ }
+
+ return NULL;
+}
+
static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
{
struct omap_mux *m = s->private;
+ struct omap_mux_partition *partition;
const char *none = "NA";
u16 val;
int mode;
- val = omap_mux_read(m->reg_offset);
+ partition = omap_mux_get_partition(m);
+ if (!partition)
+ return 0;
+
+ val = omap_mux_read(partition, m->reg_offset);
mode = val & OMAP_MUX_MODE7;
- seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n",
+ seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
m->muxnames[0], m->muxnames[mode],
- mux_phys + m->reg_offset, m->reg_offset, val,
+ partition->phys + m->reg_offset, m->reg_offset, val,
m->balls[0] ? m->balls[0] : none,
m->balls[1] ? m->balls[1] : none);
seq_printf(s, "mode: ");
#define OMAP_MUX_MAX_ARG_CHAR 7
static ssize_t omap_mux_dbg_signal_write(struct file *file,
- const char __user *user_buf,
- size_t count, loff_t *ppos)
+ const char __user *user_buf,
+ size_t count, loff_t *ppos)
{
char buf[OMAP_MUX_MAX_ARG_CHAR];
struct seq_file *seqf;
struct omap_mux *m;
unsigned long val;
int buf_size, ret;
+ struct omap_mux_partition *partition;
if (count > OMAP_MUX_MAX_ARG_CHAR)
return -EINVAL;
seqf = file->private_data;
m = seqf->private;
- omap_mux_write((u16)val, m->reg_offset);
+ partition = omap_mux_get_partition(m);
+ if (!partition)
+ return -ENODEV;
+
+ omap_mux_write(partition, (u16)val, m->reg_offset);
*ppos += count;
return count;
static struct dentry *mux_dbg_dir;
-static void __init omap_mux_dbg_init(void)
+static void __init omap_mux_dbg_create_entry(
+ struct omap_mux_partition *partition,
+ struct dentry *mux_dbg_dir)
{
struct omap_mux_entry *e;
+ list_for_each_entry(e, &partition->muxmodes, node) {
+ struct omap_mux *m = &e->mux;
+
+ (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
+ m, &omap_mux_dbg_signal_fops);
+ }
+}
+
+static void __init omap_mux_dbg_init(void)
+{
+ struct omap_mux_partition *partition;
+ static struct dentry *mux_dbg_board_dir;
+
mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
if (!mux_dbg_dir)
return;
- (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir,
- NULL, &omap_mux_dbg_board_fops);
-
- list_for_each_entry(e, &muxmodes, node) {
- struct omap_mux *m = &e->mux;
+ mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
+ if (!mux_dbg_board_dir)
+ return;
- (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
- m, &omap_mux_dbg_signal_fops);
+ list_for_each_entry(partition, &mux_partitions, node) {
+ omap_mux_dbg_create_entry(partition, mux_dbg_dir);
+ (void)debugfs_create_file(partition->name, S_IRUGO,
+ mux_dbg_board_dir, partition,
+ &omap_mux_dbg_board_fops);
}
}
/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
static int __init omap_mux_late_init(void)
{
- struct omap_mux_entry *e, *tmp;
+ struct omap_mux_partition *partition;
- list_for_each_entry_safe(e, tmp, &muxmodes, node) {
- struct omap_mux *m = &e->mux;
- u16 mode = omap_mux_read(m->reg_offset);
+ list_for_each_entry(partition, &mux_partitions, node) {
+ struct omap_mux_entry *e, *tmp;
+ list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
+ struct omap_mux *m = &e->mux;
+ u16 mode = omap_mux_read(partition, m->reg_offset);
- if (OMAP_MODE_GPIO(mode))
- continue;
+ if (OMAP_MODE_GPIO(mode))
+ continue;
#ifndef CONFIG_DEBUG_FS
- mutex_lock(&muxmode_mutex);
- list_del(&e->node);
- mutex_unlock(&muxmode_mutex);
- omap_mux_free_names(m);
- kfree(m);
+ mutex_lock(&muxmode_mutex);
+ list_del(&e->node);
+ mutex_unlock(&muxmode_mutex);
+ omap_mux_free_names(m);
+ kfree(m);
#endif
-
+ }
}
omap_mux_dbg_init();
s++;
}
if (!found)
- printk(KERN_ERR "mux: Unknown entry offset 0x%x\n",
- p->reg_offset);
+ pr_err("%s: Unknown entry offset 0x%x\n", __func__,
+ p->reg_offset);
p++;
}
}
s++;
}
if (!found)
- printk(KERN_ERR "mux: Unknown ball offset 0x%x\n",
- b->reg_offset);
+ pr_err("%s: Unknown ball offset 0x%x\n", __func__,
+ b->reg_offset);
b++;
}
}
}
static int __init omap_mux_copy_names(struct omap_mux *src,
- struct omap_mux *dst)
+ struct omap_mux *dst)
{
int i;
#endif /* CONFIG_OMAP_MUX */
-static u16 omap_mux_get_by_gpio(int gpio)
+static struct omap_mux *omap_mux_get_by_gpio(
+ struct omap_mux_partition *partition,
+ int gpio)
{
struct omap_mux_entry *e;
- u16 offset = OMAP_MUX_TERMINATOR;
+ struct omap_mux *ret = NULL;
- list_for_each_entry(e, &muxmodes, node) {
+ list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
if (m->gpio == gpio) {
- offset = m->reg_offset;
+ ret = m;
break;
}
}
- return offset;
+ return ret;
}
/* Needed for dynamic muxing of GPIO pins for off-idle */
u16 omap_mux_get_gpio(int gpio)
{
- u16 offset;
+ struct omap_mux_partition *partition;
+ struct omap_mux *m;
- offset = omap_mux_get_by_gpio(gpio);
- if (offset == OMAP_MUX_TERMINATOR) {
- printk(KERN_ERR "mux: Could not get gpio%i\n", gpio);
- return offset;
+ list_for_each_entry(partition, &mux_partitions, node) {
+ m = omap_mux_get_by_gpio(partition, gpio);
+ if (m)
+ return omap_mux_read(partition, m->reg_offset);
}
- return omap_mux_read(offset);
+ if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
+ pr_err("%s: Could not get gpio%i\n", __func__, gpio);
+
+ return OMAP_MUX_TERMINATOR;
}
/* Needed for dynamic muxing of GPIO pins for off-idle */
void omap_mux_set_gpio(u16 val, int gpio)
{
- u16 offset;
+ struct omap_mux_partition *partition;
+ struct omap_mux *m = NULL;
- offset = omap_mux_get_by_gpio(gpio);
- if (offset == OMAP_MUX_TERMINATOR) {
- printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
- return;
+ list_for_each_entry(partition, &mux_partitions, node) {
+ m = omap_mux_get_by_gpio(partition, gpio);
+ if (m) {
+ omap_mux_write(partition, val, m->reg_offset);
+ return;
+ }
}
- omap_mux_write(val, offset);
+ if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
+ pr_err("%s: Could not set gpio%i\n", __func__, gpio);
}
-static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
+static struct omap_mux * __init omap_mux_list_add(
+ struct omap_mux_partition *partition,
+ struct omap_mux *src)
{
struct omap_mux_entry *entry;
struct omap_mux *m;
#endif
mutex_lock(&muxmode_mutex);
- list_add_tail(&entry->node, &muxmodes);
+ list_add_tail(&entry->node, &partition->muxmodes);
mutex_unlock(&muxmode_mutex);
return m;
* the GPIO to mux offset mapping that is needed for dynamic muxing
* of GPIO pins for off-idle.
*/
-static void __init omap_mux_init_list(struct omap_mux *superset)
+static void __init omap_mux_init_list(struct omap_mux_partition *partition,
+ struct omap_mux *superset)
{
while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *entry;
}
#else
/* Skip pins that are not muxed as GPIO by bootloader */
- if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
+ if (!OMAP_MODE_GPIO(omap_mux_read(partition,
+ superset->reg_offset))) {
superset++;
continue;
}
#endif
- entry = omap_mux_list_add(superset);
+ entry = omap_mux_list_add(partition, superset);
if (!entry) {
- printk(KERN_ERR "mux: Could not add entry\n");
+ pr_err("%s: Could not add entry\n", __func__);
return;
}
superset++;
omap_mux_package_init_balls(package_balls, superset);
}
-static void omap_mux_init_signals(struct omap_board_mux *board_mux)
+static void omap_mux_init_signals(struct omap_mux_partition *partition,
+ struct omap_board_mux *board_mux)
{
omap_mux_set_cmdline_signals();
- omap_mux_write_array(board_mux);
+ omap_mux_write_array(partition, board_mux);
}
#else
{
}
-static void omap_mux_init_signals(struct omap_board_mux *board_mux)
+static void omap_mux_init_signals(struct omap_mux_partition *partition,
+ struct omap_board_mux *board_mux)
{
}
#endif
-int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
- struct omap_mux *superset,
- struct omap_mux *package_subset,
- struct omap_board_mux *board_mux,
- struct omap_ball *package_balls)
-{
- if (mux_base)
- return -EBUSY;
+static u32 mux_partitions_cnt;
- mux_phys = mux_pbase;
- mux_base = ioremap(mux_pbase, mux_size);
- if (!mux_base) {
- printk(KERN_ERR "mux: Could not ioremap\n");
+int __init omap_mux_init(const char *name, u32 flags,
+ u32 mux_pbase, u32 mux_size,
+ struct omap_mux *superset,
+ struct omap_mux *package_subset,
+ struct omap_board_mux *board_mux,
+ struct omap_ball *package_balls)
+{
+ struct omap_mux_partition *partition;
+
+ partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
+ if (!partition)
+ return -ENOMEM;
+
+ partition->name = name;
+ partition->flags = flags;
+ partition->size = mux_size;
+ partition->phys = mux_pbase;
+ partition->base = ioremap(mux_pbase, mux_size);
+ if (!partition->base) {
+ pr_err("%s: Could not ioremap mux partition at 0x%08x\n",
+ __func__, partition->phys);
return -ENODEV;
}
- if (cpu_is_omap24xx())
- omap_mux_flags = MUXABLE_GPIO_MODE3;
+ INIT_LIST_HEAD(&partition->muxmodes);
+
+ list_add_tail(&partition->node, &mux_partitions);
+ mux_partitions_cnt++;
+ pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__,
+ mux_partitions_cnt, partition->name, partition->flags);
omap_mux_init_package(superset, package_subset, package_balls);
- omap_mux_init_list(superset);
- omap_mux_init_signals(board_mux);
+ omap_mux_init_list(partition, superset);
+ omap_mux_init_signals(partition, board_mux);
return 0;
}
/*
* Copyright (C) 2009 Nokia
- * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2009-2010 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#include "mux2420.h"
#include "mux2430.h"
#include "mux34xx.h"
+#include "mux44xx.h"
#define OMAP_MUX_TERMINATOR 0xffff
#define OMAP_OFF_PULL_UP (1 << 13)
#define OMAP_WAKEUP_EN (1 << 14)
+/* 44xx specific mux bit defines */
+#define OMAP_WAKEUP_EVENT (1 << 15)
+
/* Active pin states */
#define OMAP_PIN_OUTPUT 0
#define OMAP_PIN_INPUT OMAP_INPUT_EN
#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
-/* Flags for omap_mux_init */
+/* Flags for omapX_mux_init */
#define OMAP_PACKAGE_MASK 0xffff
+#define OMAP_PACKAGE_CBS 8 /* 547-pin 0.40 0.40 */
+#define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */
#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */
-#define OMAP_MUX_NR_MODES 8 /* Available modes */
-#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
+#define OMAP_MUX_NR_MODES 8 /* Available modes */
+#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
+
+/*
+ * omap_mux_init flags definition:
+ *
+ * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
+ * The default value is 16 bits.
+ * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3.
+ * The default is mode4.
+ */
+#define OMAP_MUX_REG_8BIT (1 << 0)
+#define OMAP_MUX_GPIO_IN_MODE3 (1 << 1)
+
+/**
+ * struct mux_partition - contain partition related information
+ * @name: name of the current partition
+ * @flags: flags specific to this partition
+ * @phys: physical address
+ * @size: partition size
+ * @base: virtual address after ioremap
+ * @muxmodes: list of nodes that belong to a partition
+ * @node: list node for the partitions linked list
+ */
+struct omap_mux_partition {
+ const char *name;
+ u32 flags;
+ u32 phys;
+ u32 size;
+ void __iomem *base;
+ struct list_head muxmodes;
+ struct list_head node;
+};
/**
* struct omap_mux - data for omap mux register offset and it's value
* @reg_offset: mux register offset from the mux base
* @gpio: GPIO number
* @muxnames: available signal modes for a ball
+ * @balls: available balls on the package
+ * @partition: mux partition
*/
struct omap_mux {
u16 reg_offset;
return 0;
}
+static struct omap_board_mux *board_mux __initdata __maybe_unused;
+
#endif
/**
*/
void omap_mux_set_gpio(u16 val, int gpio);
+/**
+ * omap_mux_get() - get a mux partition by name
+ * @name: Name of the mux partition
+ *
+ */
+struct omap_mux_partition *omap_mux_get(const char *name);
+
/**
* omap_mux_read() - read mux register
+ * @partition: Mux partition
* @mux_offset: Offset of the mux register
*
*/
-u16 omap_mux_read(u16 mux_offset);
+u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
/**
* omap_mux_write() - write mux register
+ * @partition: Mux partition
* @val: New mux register value
* @mux_offset: Offset of the mux register
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
-void omap_mux_write(u16 val, u16 mux_offset);
+void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
/**
* omap_mux_write_array() - write an array of mux registers
+ * @partition: Mux partition
* @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
-void omap_mux_write_array(struct omap_board_mux *board_mux);
+void omap_mux_write_array(struct omap_mux_partition *p,
+ struct omap_board_mux *board_mux);
/**
* omap2420_mux_init() - initialize mux system with board specific set
*/
int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
+/**
+ * omap4_mux_init() - initialize mux system with board specific set
+ * @board_mux: Board specific mux table
+ * @flags: OMAP package type used for the board
+ */
+int omap4_mux_init(struct omap_board_mux *board_mux, int flags);
+
/**
* omap_mux_init - private mux init function, do not call
*/
-int omap_mux_init(u32 mux_pbase, u32 mux_size,
- struct omap_mux *superset,
- struct omap_mux *package_subset,
- struct omap_board_mux *board_mux,
- struct omap_ball *package_balls);
+int omap_mux_init(const char *name, u32 flags,
+ u32 mux_pbase, u32 mux_size,
+ struct omap_mux *superset,
+ struct omap_mux *package_subset,
+ struct omap_board_mux *board_mux,
+ struct omap_ball *package_balls);
+
case OMAP_PACKAGE_ZAF:
/* REVISIT: Please add data */
default:
- pr_warning("mux: No ball data available for omap2420 package\n");
+ pr_warning("%s: No ball data available for omap2420 package\n",
+ __func__);
}
- return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE,
+ return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
+ OMAP2420_CONTROL_PADCONF_MUX_PBASE,
OMAP2420_CONTROL_PADCONF_MUX_SIZE,
- omap2420_muxmodes, NULL, board_subset,
- package_balls);
+ omap2420_muxmodes, NULL, board_subset,
+ package_balls);
}
package_balls = omap2430_pop_ball;
break;
default:
- pr_warning("mux: No ball data available for omap2420 package\n");
+ pr_warning("%s: No ball data available for omap2420 package\n",
+ __func__);
}
- return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE,
+ return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
+ OMAP2430_CONTROL_PADCONF_MUX_PBASE,
OMAP2430_CONTROL_PADCONF_MUX_SIZE,
- omap2430_muxmodes, NULL, board_subset,
- package_balls);
+ omap2430_muxmodes, NULL, board_subset,
+ package_balls);
}
package_balls = omap36xx_cbp_ball;
break;
default:
- printk(KERN_ERR "mux: Unknown omap package, mux disabled\n");
+ pr_err("%s Unknown omap package, mux disabled\n", __func__);
return -EINVAL;
}
- return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE,
+ return omap_mux_init("core", 0,
+ OMAP3_CONTROL_PADCONF_MUX_PBASE,
OMAP3_CONTROL_PADCONF_MUX_SIZE,
- omap3_muxmodes, package_subset, board_subset,
- package_balls);
+ omap3_muxmodes, package_subset, board_subset,
+ package_balls);
}
--- /dev/null
+/*
+ * OMAP44xx ES1.0 pin mux definition
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com>
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .gpio = (g), \
+ .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
+}
+
+#else
+
+#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .gpio = (g), \
+}
+
+#endif
+
+#define _OMAP4_BALLENTRY(M0, bb, bt) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .balls = { bb, bt }, \
+}
+
+/*
+ * Superset of all mux modes for omap4 ES1.0
+ */
+static struct omap_mux __initdata omap4_core_muxmodes[] = {
+ _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
+ "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
+ "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
+ "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
+ "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
+ "gpio_32", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
+ "gpio_33", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
+ "gpio_34", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
+ "gpio_35", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
+ "gpio_36", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
+ "gpio_37", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
+ "gpio_38", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
+ "gpio_39", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
+ "gpio_40", "venc_656_data0", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
+ "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
+ "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
+ "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
+ "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
+ "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
+ "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
+ "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0",
+ "gpio_48", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
+ "gpio_49", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
+ "sys_ndmareq0", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
+ "gpio_51", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7",
+ "gpio_52", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
+ "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
+ "sys_ndmareq1", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
+ "sys_ndmareq2", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
+ "gpio_56", "sys_ndmareq3", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
+ "gpio_59", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
+ "gpio_60", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
+ "gpio_61", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
+ "gpio_62", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen",
+ "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0",
+ "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1",
+ "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0",
+ "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1",
+ "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
+ "gpio_65", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
+ "gpio_66", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
+ "gpio_83", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
+ "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
+ NULL, "hw_dbg20", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
+ "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
+ "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
+ "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
+ "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
+ "hsi1_acready", "mcbsp4_fsx", "gpio_87",
+ "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
+ "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
+ "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
+ "hsi1_acdata", "mcbsp4_dx", "gpio_89",
+ "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
+ "hsi1_acflag", "mcbsp4_dr", "gpio_90",
+ "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
+ "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
+ "usbb1_mm_txen", "hw_dbg27", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
+ "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
+ "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
+ "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
+ "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
+ "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
+ "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
+ "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
+ "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
+ "gpio_96", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
+ NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
+ "gpio_98", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
+ "gpio_99", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
+ "gpio_100", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
+ "gpio_101", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
+ "gpio_102", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
+ "gpio_103", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
+ "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
+ "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
+ "gpio_106", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
+ "gpio_107", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
+ "gpio_108", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
+ "gpio_109", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
+ "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
+ "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
+ "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
+ "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
+ "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
+ "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
+ "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
+ "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
+ "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
+ "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
+ NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
+ NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
+ "gpio_119", "usbb2_mm_txse0", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
+ "gpio_120", "usbb2_mm_txdat", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
+ NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
+ "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
+ "gpio_123", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
+ "gpio_124", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
+ "gpio_125", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
+ "gpio_126", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
+ "gpio_127", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
+ "gpio_128", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
+ "gpio_129", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
+ "gpio_135", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
+ "gpio_136", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
+ "gpio_138", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
+ "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
+ "slimbus2_data", "gpio_140", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
+ NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
+ "gpio_142", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
+ "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
+ "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
+ "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
+ "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
+ "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
+ "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
+ "gpio_149", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
+ "gpio_150", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL,
+ "gpio_151", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL,
+ "gpio_152", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL,
+ "gpio_153", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL,
+ "gpio_154", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL,
+ "gpio_155", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL,
+ "gpio_156", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
+ "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
+ "hsi2_cawake", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
+ "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
+ "hsi2_cadata", "dispc2_data23", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
+ "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
+ "hsi2_caflag", "dispc2_data22", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
+ "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
+ "hsi2_acready", "dispc2_data21", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
+ "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
+ "hsi2_acwake", "dispc2_data20", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
+ "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
+ "hsi2_acdata", "dispc2_data19", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
+ "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
+ "hsi2_acflag", "dispc2_data18", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
+ "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
+ "hsi2_caready", "dispc2_data15", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
+ "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
+ "mcspi3_somi", "dispc2_data14", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
+ "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
+ "mcspi3_cs0", "dispc2_data13", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
+ "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
+ "mcspi3_simo", "dispc2_data12", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
+ "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
+ "mcspi3_clk", "dispc2_data11", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
+ "gpio_169", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
+ NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL,
+ "gpio_171", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL,
+ "gpio_172", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL,
+ "gpio_173", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL,
+ "gpio_174", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL,
+ "gpio_0", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL,
+ "gpio_1", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL,
+ "gpi_175", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL,
+ "gpi_176", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL,
+ "gpi_177", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL,
+ "gpi_178", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL,
+ "gpi_2", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL,
+ "gpi_3", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx",
+ "uart2_rx", "gpio_179", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx",
+ "uart2_tx", "gpio_180", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
+ "gpio_181", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
+ "gpio_182", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
+ NULL, "hw_dbg0", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
+ NULL, "hw_dbg1", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
+ "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
+ "gpio_14", NULL, "dispc2_data10", "hw_dbg3",
+ "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
+ "gpio_15", NULL, "dispc2_data9", "hw_dbg4",
+ "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
+ "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
+ "hw_dbg5", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
+ "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
+ "dispc2_data17", "hw_dbg6", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
+ "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
+ "dispc2_hsync", "hw_dbg7", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
+ "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
+ "hw_dbg8", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
+ "uart3_cts_rctx", "gpio_20", "rfbi_we",
+ "dispc2_vsync", "hw_dbg9", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
+ NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
+ "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
+ NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
+ "hw_dbg11", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
+ NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
+ "hw_dbg12", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
+ NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
+ "hw_dbg13", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
+ "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
+ "hw_dbg14", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
+ NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
+ "hw_dbg15", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
+ "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
+ "hw_dbg16", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
+ "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
+ "hw_dbg17", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
+ "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
+ "hw_dbg18", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
+ "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
+ "hw_dbg19", "reserved"),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBL package
+ * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ * 0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
+ && defined(CONFIG_OMAP_PACKAGE_CBL)
+struct omap_ball __initdata omap4_core_cbl_ball[] = {
+ _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
+ _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
+ _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
+ _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
+ _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
+ _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
+ _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
+ _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
+ _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
+ _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
+ _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
+ _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
+ _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
+ _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
+ _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL),
+ _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
+ _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
+ _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
+ _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
+ _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
+ _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
+ _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
+ _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
+ _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
+ _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
+ _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
+ _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
+ _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
+ _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
+ _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
+ _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
+ _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
+ _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
+ _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
+ _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
+ _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
+ _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
+ _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
+ _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
+ _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
+ _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
+ _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
+ _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
+ _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
+ _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
+ _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
+ _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
+ _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
+ _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
+ _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
+ _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
+ _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
+ _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
+ _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_core_cbl_ball NULL
+#endif
+
+/*
+ * Superset of all mux modes for omap4 ES2.0
+ */
+static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
+ _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
+ "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
+ "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
+ "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
+ "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
+ "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
+ "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
+ "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
+ "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
+ "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
+ "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
+ "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
+ "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
+ "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
+ "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
+ "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
+ "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
+ "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
+ "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
+ "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
+ "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0",
+ "gpio_48", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
+ "gpio_49", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
+ "sys_ndmareq0", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
+ "gpio_51", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8",
+ "c2c_dataout7", "gpio_52", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
+ "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
+ "sys_ndmareq1", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
+ "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
+ "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
+ "gpio_59", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
+ "gpio_60", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
+ "gpio_61", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
+ "gpio_62", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen",
+ "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0",
+ "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1",
+ "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0",
+ "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1",
+ "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
+ "gpio_65", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
+ "gpio_66", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
+ "gpio_83", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
+ "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
+ NULL, "hw_dbg20", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
+ "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
+ "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
+ "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
+ "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
+ "hsi1_acready", "mcbsp4_fsx", "gpio_87",
+ "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
+ "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
+ "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
+ "hsi1_acdata", "mcbsp4_dx", "gpio_89",
+ "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
+ "hsi1_acflag", "mcbsp4_dr", "gpio_90",
+ "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
+ "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
+ "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
+ "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
+ "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
+ "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
+ "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
+ "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
+ "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
+ "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
+ "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
+ "gpio_96", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
+ NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
+ "gpio_98", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
+ "gpio_99", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
+ "gpio_100", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
+ "gpio_101", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
+ "gpio_102", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
+ "gpio_103", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
+ "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
+ "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
+ "gpio_106", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
+ "gpio_107", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
+ "gpio_108", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
+ "gpio_109", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
+ "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
+ "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
+ "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
+ "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
+ "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
+ "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
+ "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
+ "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
+ "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
+ "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
+ NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
+ NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
+ "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
+ "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
+ "abe_mcasp_axr", "gpio_121", NULL,
+ "dmtimer11_pwm_evt", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
+ "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt",
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
+ "gpio_123", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
+ "gpio_124", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
+ "gpio_125", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
+ "gpio_126", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
+ "gpio_127", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
+ "gpio_128", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
+ "gpio_129", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
+ "gpio_135", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
+ "gpio_136", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
+ "gpio_138", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
+ "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
+ "slimbus2_data", "gpio_140", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
+ NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
+ "gpio_142", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
+ "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
+ "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
+ "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk",
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
+ "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd",
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
+ "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0",
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
+ "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1",
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
+ "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
+ "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk",
+ "kpd_col6", "gpio_151", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd",
+ "kpd_col7", "gpio_152", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0",
+ "kpd_row6", "gpio_153", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3",
+ "kpd_row7", "gpio_154", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8",
+ "gpio_155", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8",
+ "gpio_156", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
+ "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
+ "hsi2_cawake", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
+ "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
+ "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
+ "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
+ "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
+ "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
+ "hsi2_acready", "dispc2_data21", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
+ "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
+ "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
+ "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
+ "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
+ "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
+ "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
+ "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
+ "hsi2_caready", "dispc2_data15", "rfbi_data15",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
+ "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
+ "mcspi3_somi", "dispc2_data14", "rfbi_data14",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
+ "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
+ "mcspi3_cs0", "dispc2_data13", "rfbi_data13",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
+ "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
+ "mcspi3_simo", "dispc2_data12", "rfbi_data12",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
+ "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
+ "mcspi3_clk", "dispc2_data11", "rfbi_data11",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
+ "gpio_169", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
+ NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL,
+ "gpio_171", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL,
+ "gpio_172", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL,
+ "gpio_173", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL,
+ "gpio_174", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL,
+ "gpio_175", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL,
+ "gpio_176", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL,
+ "gpio_177", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL,
+ "gpio_178", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx",
+ "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx",
+ "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
+ "gpio_181", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
+ "gpio_182", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
+ NULL, "hw_dbg0", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
+ NULL, "hw_dbg1", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
+ "gpio_13", NULL, "dispc2_fid", "hw_dbg2",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
+ "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
+ "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
+ "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
+ "hw_dbg5", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
+ "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
+ "dispc2_data17", "hw_dbg6", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
+ "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
+ "dispc2_hsync", "hw_dbg7", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
+ "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
+ "hw_dbg8", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
+ "uart3_cts_rctx", "gpio_20", "rfbi_we",
+ "dispc2_vsync", "hw_dbg9", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
+ NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
+ NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
+ "hw_dbg11", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
+ NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
+ "hw_dbg12", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
+ NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
+ "hw_dbg13", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
+ "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
+ "hw_dbg14", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
+ NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
+ "hw_dbg15", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
+ "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
+ "hw_dbg16", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
+ "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
+ "hw_dbg17", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
+ "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
+ "hw_dbg18", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
+ "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
+ "hw_dbg19", "safe_mode"),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBS package
+ * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ * 0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
+ && defined(CONFIG_OMAP_PACKAGE_CBS)
+struct omap_ball __initdata omap4_core_cbs_ball[] = {
+ _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
+ _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
+ _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
+ _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
+ _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
+ _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
+ _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
+ _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
+ _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
+ _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
+ _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
+ _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
+ _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
+ _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
+ _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL),
+ _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
+ _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
+ _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
+ _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
+ _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
+ _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
+ _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
+ _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
+ _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
+ _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
+ _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
+ _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
+ _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
+ _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
+ _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
+ _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
+ _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
+ _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
+ _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
+ _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
+ _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
+ _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
+ _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
+ _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
+ _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
+ _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
+ _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
+ _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
+ _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
+ _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
+ _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
+ _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
+ _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
+ _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
+ _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
+ _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
+ _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
+ _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL),
+ _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL),
+ _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL),
+ _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL),
+ _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL),
+ _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
+ _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
+ _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_core_cbs_ball NULL
+#endif
+
+/*
+ * Superset of all mux modes for omap4
+ */
+static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
+ _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
+ "c2c_wakereqin", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
+ "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req",
+ "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req",
+ "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req",
+ "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout",
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out",
+ NULL, "gpio_wk7", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL,
+ "gpio_wk8", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL,
+ NULL, "gpio_wk29", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL,
+ "gpio_wk9", "c2c_wakereqout", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL,
+ "gpio_wk10", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL,
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBL & CBS package - wakeup partition
+ * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ * 0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
+ && defined(CONFIG_OMAP_PACKAGE_CBL)
+struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = {
+ _OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
+ _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
+ _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
+ _OMAP4_BALLENTRY(SIM_CD, "j1", NULL),
+ _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL),
+ _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL),
+ _OMAP4_BALLENTRY(SR_SDA, "af9", NULL),
+ _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL),
+ _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL),
+ _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL),
+ _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL),
+ _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL),
+ _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL),
+ _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL),
+ _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL),
+ _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL),
+ _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL),
+ _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL),
+ _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL),
+ _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_wkup_cbl_cbs_ball NULL
+#endif
+
+int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags)
+{
+ struct omap_ball *package_balls_core;
+ struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball;
+ struct omap_mux *core_muxmodes;
+ int ret;
+
+ switch (flags & OMAP_PACKAGE_MASK) {
+ case OMAP_PACKAGE_CBL:
+ pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__);
+ package_balls_core = omap4_core_cbl_ball;
+ core_muxmodes = omap4_core_muxmodes;
+ break;
+ case OMAP_PACKAGE_CBS:
+ pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__);
+ package_balls_core = omap4_core_cbs_ball;
+ core_muxmodes = omap4_es2_core_muxmodes;
+ break;
+ default:
+ pr_err("%s: Unknown omap package, mux disabled\n", __func__);
+ return -EINVAL;
+ }
+
+ ret = omap_mux_init("core",
+ OMAP_MUX_GPIO_IN_MODE3,
+ OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
+ OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
+ core_muxmodes, NULL, board_subset,
+ package_balls_core);
+ if (ret)
+ return ret;
+
+ ret = omap_mux_init("wkup",
+ OMAP_MUX_GPIO_IN_MODE3,
+ OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
+ OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
+ omap4_wkup_muxmodes, NULL, board_subset,
+ package_balls_wkup);
+
+ return ret;
+}
+
--- /dev/null
+/*
+ * OMAP44xx MUX registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
+
+#define OMAP4_MUX(M0, mux_value) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .value = (mux_value), \
+}
+
+/* ctrl_module_pad_core base address */
+#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000
+
+/* ctrl_module_pad_core registers offset */
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096
+#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098
+#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba
+#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc
+#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be
+#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c
+#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116
+#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118
+#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a
+#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c
+#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e
+#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120
+#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122
+#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124
+#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126
+#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128
+#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a
+#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c
+#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e
+#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e
+#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140
+#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142
+#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144
+#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a
+#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c
+#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176
+#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178
+#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c
+#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e
+#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4
+
+/* ES2.0 only */
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET 0x008e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET 0x0090
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET 0x0092
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET 0x0094
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET 0x0096
+
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET 0x017c
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET 0x017e
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET 0x0180
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET 0x0182
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET 0x0184
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET 0x0186
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET 0x0188
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET 0x018a
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET 0x018c
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET 0x018e
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET 0x0190
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET 0x0192
+
+
+#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \
+ (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \
+ - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
+
+/* ctrl_module_pad_wkup base address */
+#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000
+
+/* ctrl_module_pad_wkup registers offset */
+#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040
+#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042
+#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044
+#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046
+#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048
+#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a
+#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c
+#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e
+#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c
+#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e
+#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060
+#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062
+#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064
+#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a
+#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e
+#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076
+
+#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \
+ (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \
+ - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
+
+#endif
.name = "isp",
.nr_tlb_entries = 8,
.clk_name = "cam_ick",
+ .da_start = 0x0,
+ .da_end = 0xFFFFF000,
},
},
-#if defined(CONFIG_MPU_BRIDGE_IOMMU)
+#if defined(CONFIG_OMAP_IOMMU_IVA2)
{
.base = 0x5d000000,
.irq = 28,
.name = "iva2",
.nr_tlb_entries = 32,
.clk_name = "iva2_ck",
+ .da_start = 0x11000000,
+ .da_end = 0xFFFFF000,
},
},
#endif
.name = "ducati",
.nr_tlb_entries = 32,
.clk_name = "ducati_ick",
+ .da_start = 0x0,
+ .da_end = 0xFFFFF000,
},
},
#if defined(CONFIG_MPU_TESLA_IOMMU)
.name = "tesla",
.nr_tlb_entries = 32,
.clk_name = "tesla_ick",
+ .da_start = 0x0,
+ .da_end = 0xFFFFF000,
},
},
#endif
#include <plat/cpu.h>
#include <plat/dma.h>
#include <plat/serial.h>
+#include <plat/i2c.h>
+#include <plat/gpio.h>
#include "omap_hwmod_common_data.h"
-#include "prm-regbits-24xx.h"
#include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
/*
* OMAP2420 hardware module integration data
static struct omap_hwmod omap2420_l3_main_hwmod;
static struct omap_hwmod omap2420_l4_core_hwmod;
static struct omap_hwmod omap2420_wd_timer2_hwmod;
+static struct omap_hwmod omap2420_gpio1_hwmod;
+static struct omap_hwmod omap2420_gpio2_hwmod;
+static struct omap_hwmod omap2420_gpio3_hwmod;
+static struct omap_hwmod omap2420_gpio4_hwmod;
/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
static struct omap_hwmod omap2420_uart1_hwmod;
static struct omap_hwmod omap2420_uart2_hwmod;
static struct omap_hwmod omap2420_uart3_hwmod;
+static struct omap_hwmod omap2420_i2c1_hwmod;
+static struct omap_hwmod omap2420_i2c2_hwmod;
/* L4_CORE -> L4_WKUP interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN 128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
+ {
+ .pa_start = 0x48070000,
+ .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_i2c1_hwmod,
+ .clk = "i2c1_ick",
+ .addr = omap2420_i2c1_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
+ {
+ .pa_start = 0x48072000,
+ .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_i2c2_hwmod,
+ .clk = "i2c2_ick",
+ .addr = omap2420_i2c2_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* Slave interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
&omap2420_l3_main__l4_core,
&omap2_l4_core__uart1,
&omap2_l4_core__uart2,
&omap2_l4_core__uart3,
+ &omap2420_l4_core__i2c1,
+ &omap2420_l4_core__i2c2
};
/* L4 CORE */
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x20,
+ .syss_offs = 0x10,
+ .sysc_flags = SYSC_HAS_SOFTRESET,
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr;
+
+/* I2C1 */
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
+ &omap2420_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap2420_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = i2c1_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
+ .sdma_reqs = i2c1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2c1_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP2420_EN_I2C1_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
+ },
+ },
+ .slaves = omap2420_i2c1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
+ .class = &i2c_class,
+ .dev_attr = &i2c_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ .flags = HWMOD_16BIT_REG,
+};
+
+/* I2C2 */
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
+ &omap2420_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap2420_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = i2c2_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
+ .sdma_reqs = i2c2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2c2_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP2420_EN_I2C2_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
+ },
+ },
+ .slaves = omap2420_i2c2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
+ .class = &i2c_class,
+ .dev_attr = &i2c_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ .flags = HWMOD_16BIT_REG,
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
+ {
+ .pa_start = 0x48018000,
+ .pa_end = 0x480181ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
+ .master = &omap2420_l4_wkup_hwmod,
+ .slave = &omap2420_gpio1_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2420_gpio1_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio2 */
+static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
+ {
+ .pa_start = 0x4801a000,
+ .pa_end = 0x4801a1ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
+ .master = &omap2420_l4_wkup_hwmod,
+ .slave = &omap2420_gpio2_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2420_gpio2_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio3 */
+static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
+ {
+ .pa_start = 0x4801c000,
+ .pa_end = 0x4801c1ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
+ .master = &omap2420_l4_wkup_hwmod,
+ .slave = &omap2420_gpio3_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2420_gpio3_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio4 */
+static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
+ {
+ .pa_start = 0x4801e000,
+ .pa_end = 0x4801e1ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
+ .master = &omap2420_l4_wkup_hwmod,
+ .slave = &omap2420_gpio4_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2420_gpio4_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = false,
+};
+
+static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &omap242x_gpio_sysc,
+ .rev = 0,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
+ { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
+ &omap2420_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod omap2420_gpio1_hwmod = {
+ .name = "gpio1",
+ .mpu_irqs = omap242x_gpio1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+ },
+ },
+ .slaves = omap2420_gpio1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
+ .class = &omap242x_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
+ { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
+ &omap2420_l4_wkup__gpio2,
+};
+
+static struct omap_hwmod omap2420_gpio2_hwmod = {
+ .name = "gpio2",
+ .mpu_irqs = omap242x_gpio2_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+ },
+ },
+ .slaves = omap2420_gpio2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
+ .class = &omap242x_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
+ { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
+ &omap2420_l4_wkup__gpio3,
+};
+
+static struct omap_hwmod omap2420_gpio3_hwmod = {
+ .name = "gpio3",
+ .mpu_irqs = omap242x_gpio3_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+ },
+ },
+ .slaves = omap2420_gpio3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
+ .class = &omap242x_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* gpio4 */
+static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
+ { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
+ &omap2420_l4_wkup__gpio4,
+};
+
+static struct omap_hwmod omap2420_gpio4_hwmod = {
+ .name = "gpio4",
+ .mpu_irqs = omap242x_gpio4_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+ },
+ },
+ .slaves = omap2420_gpio4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
+ .class = &omap242x_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
static __initdata struct omap_hwmod *omap2420_hwmods[] = {
&omap2420_l3_main_hwmod,
&omap2420_l4_core_hwmod,
&omap2420_uart1_hwmod,
&omap2420_uart2_hwmod,
&omap2420_uart3_hwmod,
+ &omap2420_i2c1_hwmod,
+ &omap2420_i2c2_hwmod,
+
+ /* gpio class */
+ &omap2420_gpio1_hwmod,
+ &omap2420_gpio2_hwmod,
+ &omap2420_gpio3_hwmod,
+ &omap2420_gpio4_hwmod,
NULL,
};
{
return omap_hwmod_init(omap2420_hwmods);
}
-
-
#include <plat/cpu.h>
#include <plat/dma.h>
#include <plat/serial.h>
+#include <plat/i2c.h>
+#include <plat/gpio.h>
#include "omap_hwmod_common_data.h"
static struct omap_hwmod omap2430_l3_main_hwmod;
static struct omap_hwmod omap2430_l4_core_hwmod;
static struct omap_hwmod omap2430_wd_timer2_hwmod;
+static struct omap_hwmod omap2430_gpio1_hwmod;
+static struct omap_hwmod omap2430_gpio2_hwmod;
+static struct omap_hwmod omap2430_gpio3_hwmod;
+static struct omap_hwmod omap2430_gpio4_hwmod;
+static struct omap_hwmod omap2430_gpio5_hwmod;
/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
static struct omap_hwmod omap2430_uart1_hwmod;
static struct omap_hwmod omap2430_uart2_hwmod;
static struct omap_hwmod omap2430_uart3_hwmod;
+static struct omap_hwmod omap2430_i2c1_hwmod;
+static struct omap_hwmod omap2430_i2c2_hwmod;
+
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN 128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
+ {
+ .pa_start = 0x48070000,
+ .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_i2c1_hwmod,
+ .clk = "i2c1_ick",
+ .addr = omap2430_i2c1_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
+ {
+ .pa_start = 0x48072000,
+ .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_i2c2_hwmod,
+ .clk = "i2c2_ick",
+ .addr = omap2430_i2c2_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
/* L4_CORE -> L4_WKUP interface */
static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x20,
+ .syss_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
+};
+
+/* I2C1 */
+
+static struct omap_i2c_dev_attr i2c1_dev_attr = {
+ .fifo_depth = 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
+ &omap2430_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap2430_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = i2c1_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
+ .sdma_reqs = i2c1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2chs1_fck",
+ .prcm = {
+ .omap2 = {
+ /*
+ * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
+ * I2CHS IP's do not follow the usual pattern.
+ * prcm_reg_id alone cannot be used to program
+ * the iclk and fclk. Needs to be handled using
+ * additonal flags when clk handling is moved
+ * to hwmod framework.
+ */
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
+ },
+ },
+ .slaves = omap2430_i2c1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
+ .class = &i2c_class,
+ .dev_attr = &i2c1_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* I2C2 */
+
+static struct omap_i2c_dev_attr i2c2_dev_attr = {
+ .fifo_depth = 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
+ &omap2430_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap2430_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = i2c2_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
+ .sdma_reqs = i2c2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2chs2_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
+ },
+ },
+ .slaves = omap2430_i2c2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
+ .class = &i2c_class,
+ .dev_attr = &i2c2_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
+ {
+ .pa_start = 0x4900C000,
+ .pa_end = 0x4900C1ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
+ .master = &omap2430_l4_wkup_hwmod,
+ .slave = &omap2430_gpio1_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio1_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio2 */
+static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
+ {
+ .pa_start = 0x4900E000,
+ .pa_end = 0x4900E1ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
+ .master = &omap2430_l4_wkup_hwmod,
+ .slave = &omap2430_gpio2_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio2_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio3 */
+static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
+ {
+ .pa_start = 0x49010000,
+ .pa_end = 0x490101ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
+ .master = &omap2430_l4_wkup_hwmod,
+ .slave = &omap2430_gpio3_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio3_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio4 */
+static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
+ {
+ .pa_start = 0x49012000,
+ .pa_end = 0x490121ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
+ .master = &omap2430_l4_wkup_hwmod,
+ .slave = &omap2430_gpio4_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio4_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> gpio5 */
+static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
+ {
+ .pa_start = 0x480B6000,
+ .pa_end = 0x480B61ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_gpio5_hwmod,
+ .clk = "gpio5_ick",
+ .addr = omap2430_gpio5_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = false,
+};
+
+static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &omap243x_gpio_sysc,
+ .rev = 0,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
+ { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
+ &omap2430_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod omap2430_gpio1_hwmod = {
+ .name = "gpio1",
+ .mpu_irqs = omap243x_gpio1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ },
+ },
+ .slaves = omap2430_gpio1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
+ .class = &omap243x_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
+ { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
+ &omap2430_l4_wkup__gpio2,
+};
+
+static struct omap_hwmod omap2430_gpio2_hwmod = {
+ .name = "gpio2",
+ .mpu_irqs = omap243x_gpio2_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+ },
+ },
+ .slaves = omap2430_gpio2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
+ .class = &omap243x_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
+ { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
+ &omap2430_l4_wkup__gpio3,
+};
+
+static struct omap_hwmod omap2430_gpio3_hwmod = {
+ .name = "gpio3",
+ .mpu_irqs = omap243x_gpio3_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+ },
+ },
+ .slaves = omap2430_gpio3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
+ .class = &omap243x_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio4 */
+static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
+ { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
+ &omap2430_l4_wkup__gpio4,
+};
+
+static struct omap_hwmod omap2430_gpio4_hwmod = {
+ .name = "gpio4",
+ .mpu_irqs = omap243x_gpio4_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+ },
+ },
+ .slaves = omap2430_gpio4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
+ .class = &omap243x_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio5 */
+static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
+ { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
+ &omap2430_l4_core__gpio5,
+};
+
+static struct omap_hwmod omap2430_gpio5_hwmod = {
+ .name = "gpio5",
+ .mpu_irqs = omap243x_gpio5_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
+ .main_clk = "gpio5_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 2,
+ .module_bit = OMAP2430_EN_GPIO5_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 2,
+ .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
+ },
+ },
+ .slaves = omap2430_gpio5_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
+ .class = &omap243x_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
static __initdata struct omap_hwmod *omap2430_hwmods[] = {
&omap2430_l3_main_hwmod,
&omap2430_l4_core_hwmod,
&omap2430_uart1_hwmod,
&omap2430_uart2_hwmod,
&omap2430_uart3_hwmod,
+ &omap2430_i2c1_hwmod,
+ &omap2430_i2c2_hwmod,
+
+ /* gpio class */
+ &omap2430_gpio1_hwmod,
+ &omap2430_gpio2_hwmod,
+ &omap2430_gpio3_hwmod,
+ &omap2430_gpio4_hwmod,
+ &omap2430_gpio5_hwmod,
NULL,
};
{
return omap_hwmod_init(omap2430_hwmods);
}
-
-
#include <plat/cpu.h>
#include <plat/dma.h>
#include <plat/serial.h>
+#include <plat/l4_3xxx.h>
+#include <plat/i2c.h>
+#include <plat/gpio.h>
#include "omap_hwmod_common_data.h"
static struct omap_hwmod omap3xxx_l4_core_hwmod;
static struct omap_hwmod omap3xxx_l4_per_hwmod;
static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
+static struct omap_hwmod omap3xxx_i2c1_hwmod;
+static struct omap_hwmod omap3xxx_i2c2_hwmod;
+static struct omap_hwmod omap3xxx_i2c3_hwmod;
+static struct omap_hwmod omap3xxx_gpio1_hwmod;
+static struct omap_hwmod omap3xxx_gpio2_hwmod;
+static struct omap_hwmod omap3xxx_gpio3_hwmod;
+static struct omap_hwmod omap3xxx_gpio4_hwmod;
+static struct omap_hwmod omap3xxx_gpio5_hwmod;
+static struct omap_hwmod omap3xxx_gpio6_hwmod;
/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN 128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
+ {
+ .pa_start = 0x48070000,
+ .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_i2c1_hwmod,
+ .clk = "i2c1_ick",
+ .addr = omap3xxx_i2c1_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
+ .l4_prot_group = 7,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
+ {
+ .pa_start = 0x48072000,
+ .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_i2c2_hwmod,
+ .clk = "i2c2_ick",
+ .addr = omap3xxx_i2c2_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
+ .l4_prot_group = 7,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C3 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
+ {
+ .pa_start = 0x48060000,
+ .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_i2c3_hwmod,
+ .clk = "i2c3_ick",
+ .addr = omap3xxx_i2c3_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
+ .l4_prot_group = 7,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* Slave interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
&omap3xxx_l3_main__l4_core,
&omap3xxx_l4_core__l4_wkup,
&omap3_l4_core__uart1,
&omap3_l4_core__uart2,
+ &omap3_l4_core__i2c1,
+ &omap3_l4_core__i2c2,
+ &omap3_l4_core__i2c3,
};
/* L4 CORE */
.sysc_fields = &omap_hwmod_sysc_type1,
};
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x20,
+ .syss_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap3xxx_wd_timer_sysc,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
+};
+
+/* I2C1 */
+
+static struct omap_i2c_dev_attr i2c1_dev_attr = {
+ .fifo_depth = 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+ &omap3_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = i2c1_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
+ .sdma_reqs = i2c1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2c1_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_I2C1_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_i2c1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
+ .class = &i2c_class,
+ .dev_attr = &i2c1_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* I2C2 */
+
+static struct omap_i2c_dev_attr i2c2_dev_attr = {
+ .fifo_depth = 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+ &omap3_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = i2c2_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
+ .sdma_reqs = i2c2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2c2_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_I2C2_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_i2c2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
+ .class = &i2c_class,
+ .dev_attr = &i2c2_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* I2C3 */
+
+static struct omap_i2c_dev_attr i2c3_dev_attr = {
+ .fifo_depth = 64, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+ { .irq = INT_34XX_I2C3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
+ { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
+ &omap3_l4_core__i2c3,
+};
+
+static struct omap_hwmod omap3xxx_i2c3_hwmod = {
+ .name = "i2c3",
+ .mpu_irqs = i2c3_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
+ .sdma_reqs = i2c3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
+ .main_clk = "i2c3_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_I2C3_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_i2c3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
+ .class = &i2c_class,
+ .dev_attr = &i2c3_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
+ {
+ .pa_start = 0x48310000,
+ .pa_end = 0x483101ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
+ .master = &omap3xxx_l4_wkup_hwmod,
+ .slave = &omap3xxx_gpio1_hwmod,
+ .addr = omap3xxx_gpio1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
+ {
+ .pa_start = 0x49050000,
+ .pa_end = 0x490501ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio2_hwmod,
+ .addr = omap3xxx_gpio2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
+ {
+ .pa_start = 0x49052000,
+ .pa_end = 0x490521ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio3_hwmod,
+ .addr = omap3xxx_gpio3_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
+ {
+ .pa_start = 0x49054000,
+ .pa_end = 0x490541ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio4_hwmod,
+ .addr = omap3xxx_gpio4_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
+ {
+ .pa_start = 0x49056000,
+ .pa_end = 0x490561ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio5_hwmod,
+ .addr = omap3xxx_gpio5_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
+ {
+ .pa_start = 0x49058000,
+ .pa_end = 0x490581ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio6_hwmod,
+ .addr = omap3xxx_gpio6_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &omap3xxx_gpio_sysc,
+ .rev = 1,
+};
+
+/* gpio_dev_attr*/
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
+ { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
+ &omap3xxx_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod omap3xxx_gpio1_hwmod = {
+ .name = "gpio1",
+ .mpu_irqs = omap3xxx_gpio1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
+ .main_clk = "gpio1_ick",
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPIO1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_gpio1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
+ { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
+ &omap3xxx_l4_per__gpio2,
+};
+
+static struct omap_hwmod omap3xxx_gpio2_hwmod = {
+ .name = "gpio2",
+ .mpu_irqs = omap3xxx_gpio2_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
+ .main_clk = "gpio2_ick",
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPIO2_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_gpio2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
+ { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio3_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
+ &omap3xxx_l4_per__gpio3,
+};
+
+static struct omap_hwmod omap3xxx_gpio3_hwmod = {
+ .name = "gpio3",
+ .mpu_irqs = omap3xxx_gpio3_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
+ .main_clk = "gpio3_ick",
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPIO3_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_gpio3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio4 */
+static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
+ { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio4_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
+ &omap3xxx_l4_per__gpio4,
+};
+
+static struct omap_hwmod omap3xxx_gpio4_hwmod = {
+ .name = "gpio4",
+ .mpu_irqs = omap3xxx_gpio4_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
+ .main_clk = "gpio4_ick",
+ .opt_clks = gpio4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPIO4_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_gpio4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio5 */
+static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
+ { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
+};
+
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio5_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
+ &omap3xxx_l4_per__gpio5,
+};
+
+static struct omap_hwmod omap3xxx_gpio5_hwmod = {
+ .name = "gpio5",
+ .mpu_irqs = omap3xxx_gpio5_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
+ .main_clk = "gpio5_ick",
+ .opt_clks = gpio5_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPIO5_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_gpio5_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio6 */
+static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
+ { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
+};
+
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio6_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
+ &omap3xxx_l4_per__gpio6,
+};
+
+static struct omap_hwmod omap3xxx_gpio6_hwmod = {
+ .name = "gpio6",
+ .mpu_irqs = omap3xxx_gpio6_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
+ .main_clk = "gpio6_ick",
+ .opt_clks = gpio6_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPIO6_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_gpio6_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_l3_main_hwmod,
&omap3xxx_l4_core_hwmod,
&omap3xxx_uart2_hwmod,
&omap3xxx_uart3_hwmod,
&omap3xxx_uart4_hwmod,
+ &omap3xxx_i2c1_hwmod,
+ &omap3xxx_i2c2_hwmod,
+ &omap3xxx_i2c3_hwmod,
+
+ /* gpio class */
+ &omap3xxx_gpio1_hwmod,
+ &omap3xxx_gpio2_hwmod,
+ &omap3xxx_gpio3_hwmod,
+ &omap3xxx_gpio4_hwmod,
+ &omap3xxx_gpio5_hwmod,
+ &omap3xxx_gpio6_hwmod,
NULL,
};
#include <plat/omap_hwmod.h>
#include <plat/cpu.h>
+#include <plat/gpio.h>
#include "omap_hwmod_common_data.h"
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+/*
+ * 'i2c' class
+ * multimaster high-speed i2c controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0090,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
+ .name = "i2c",
+ .sysc = &omap44xx_i2c_sysc,
+};
+
+/* i2c1 */
+static struct omap_hwmod omap44xx_i2c1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
+ { .irq = 56 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
+ {
+ .pa_start = 0x48070000,
+ .pa_end = 0x480700ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_i2c1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
+ &omap44xx_l4_per__i2c1,
+};
+
+static struct omap_hwmod omap44xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .class = &omap44xx_i2c_hwmod_class,
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
+ .sdma_reqs = omap44xx_i2c1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
+ .main_clk = "i2c1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_i2c1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c2 */
+static struct omap_hwmod omap44xx_i2c2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
+ { .irq = 57 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
+ {
+ .pa_start = 0x48072000,
+ .pa_end = 0x480720ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_i2c2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
+ &omap44xx_l4_per__i2c2,
+};
+
+static struct omap_hwmod omap44xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .class = &omap44xx_i2c_hwmod_class,
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c2_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
+ .sdma_reqs = omap44xx_i2c2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
+ .main_clk = "i2c2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_i2c2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c3 */
+static struct omap_hwmod omap44xx_i2c3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
+ { .irq = 61 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
+ {
+ .pa_start = 0x48060000,
+ .pa_end = 0x480600ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_i2c3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c3_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
+ &omap44xx_l4_per__i2c3,
+};
+
+static struct omap_hwmod omap44xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .class = &omap44xx_i2c_hwmod_class,
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c3_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
+ .sdma_reqs = omap44xx_i2c3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
+ .main_clk = "i2c3_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_i2c3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c4 */
+static struct omap_hwmod omap44xx_i2c4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
+ { .irq = 62 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
+ {
+ .pa_start = 0x48350000,
+ .pa_end = 0x483500ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_i2c4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c4_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
+ &omap44xx_l4_per__i2c4,
+};
+
+static struct omap_hwmod omap44xx_i2c4_hwmod = {
+ .name = "i2c4",
+ .class = &omap44xx_i2c_hwmod_class,
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c4_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
+ .sdma_reqs = omap44xx_i2c4_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
+ .main_clk = "i2c4_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_i2c4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
/*
* 'mpu_bus' class
* instance(s): mpu_private
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &omap44xx_gpio_sysc,
+ .rev = 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod omap44xx_gpio1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
+ { .irq = 29 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
+ {
+ .pa_start = 0x4a310000,
+ .pa_end = 0x4a3101ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_gpio1_hwmod,
+ .addr = omap44xx_gpio1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
+ &omap44xx_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "sys_32k_ck" },
+};
+
+static struct omap_hwmod omap44xx_gpio1_hwmod = {
+ .name = "gpio1",
+ .class = &omap44xx_gpio_hwmod_class,
+ .mpu_irqs = omap44xx_gpio1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
+ .main_clk = "gpio1_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+ .slaves = omap44xx_gpio1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio2 */
+static struct omap_hwmod omap44xx_gpio2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
+ { .irq = 30 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
+ {
+ .pa_start = 0x48055000,
+ .pa_end = 0x480551ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_gpio2_hwmod,
+ .addr = omap44xx_gpio2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
+ &omap44xx_l4_per__gpio2,
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "sys_32k_ck" },
+};
+
+static struct omap_hwmod omap44xx_gpio2_hwmod = {
+ .name = "gpio2",
+ .class = &omap44xx_gpio_hwmod_class,
+ .mpu_irqs = omap44xx_gpio2_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
+ .main_clk = "gpio2_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+ .slaves = omap44xx_gpio2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio3 */
+static struct omap_hwmod omap44xx_gpio3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
+ { .irq = 31 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
+ {
+ .pa_start = 0x48057000,
+ .pa_end = 0x480571ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_gpio3_hwmod,
+ .addr = omap44xx_gpio3_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
+ &omap44xx_l4_per__gpio3,
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "sys_32k_ck" },
+};
+
+static struct omap_hwmod omap44xx_gpio3_hwmod = {
+ .name = "gpio3",
+ .class = &omap44xx_gpio_hwmod_class,
+ .mpu_irqs = omap44xx_gpio3_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
+ .main_clk = "gpio3_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+ .slaves = omap44xx_gpio3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio4 */
+static struct omap_hwmod omap44xx_gpio4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
+ { .irq = 32 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
+ {
+ .pa_start = 0x48059000,
+ .pa_end = 0x480591ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_gpio4_hwmod,
+ .addr = omap44xx_gpio4_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
+ &omap44xx_l4_per__gpio4,
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+ { .role = "dbclk", .clk = "sys_32k_ck" },
+};
+
+static struct omap_hwmod omap44xx_gpio4_hwmod = {
+ .name = "gpio4",
+ .class = &omap44xx_gpio_hwmod_class,
+ .mpu_irqs = omap44xx_gpio4_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
+ .main_clk = "gpio4_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+ },
+ },
+ .opt_clks = gpio4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+ .slaves = omap44xx_gpio4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio5 */
+static struct omap_hwmod omap44xx_gpio5_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
+ { .irq = 33 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
+ {
+ .pa_start = 0x4805b000,
+ .pa_end = 0x4805b1ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_gpio5_hwmod,
+ .addr = omap44xx_gpio5_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio5 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
+ &omap44xx_l4_per__gpio5,
+};
+
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+ { .role = "dbclk", .clk = "sys_32k_ck" },
+};
+
+static struct omap_hwmod omap44xx_gpio5_hwmod = {
+ .name = "gpio5",
+ .class = &omap44xx_gpio_hwmod_class,
+ .mpu_irqs = omap44xx_gpio5_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
+ .main_clk = "gpio5_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+ },
+ },
+ .opt_clks = gpio5_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+ .slaves = omap44xx_gpio5_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio6 */
+static struct omap_hwmod omap44xx_gpio6_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
+ { .irq = 34 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
+ {
+ .pa_start = 0x4805d000,
+ .pa_end = 0x4805d1ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_gpio6_hwmod,
+ .addr = omap44xx_gpio6_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio6 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
+ &omap44xx_l4_per__gpio6,
+};
+
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+ { .role = "dbclk", .clk = "sys_32k_ck" },
+};
+
+static struct omap_hwmod omap44xx_gpio6_hwmod = {
+ .name = "gpio6",
+ .class = &omap44xx_gpio_hwmod_class,
+ .mpu_irqs = omap44xx_gpio6_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
+ .main_clk = "gpio6_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+ },
+ },
+ .opt_clks = gpio6_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+ .slaves = omap44xx_gpio6_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* dmm class */
&omap44xx_dmm_hwmod,
&omap44xx_l4_cfg_hwmod,
&omap44xx_l4_per_hwmod,
&omap44xx_l4_wkup_hwmod,
+ /* i2c class */
+ &omap44xx_i2c1_hwmod,
+ &omap44xx_i2c2_hwmod,
+ &omap44xx_i2c3_hwmod,
+ &omap44xx_i2c4_hwmod,
/* mpu_bus class */
&omap44xx_mpu_private_hwmod,
+ /* gpio class */
+ &omap44xx_gpio1_hwmod,
+ &omap44xx_gpio2_hwmod,
+ &omap44xx_gpio3_hwmod,
+ &omap44xx_gpio4_hwmod,
+ &omap44xx_gpio5_hwmod,
+ &omap44xx_gpio6_hwmod,
+
/* mpu class */
&omap44xx_mpu_hwmod,
/* wd_timer class */
* 3430s upto ES3.0 and 3630ES1.0. Hence this feature
* needs to be disabled on these chips.
* Refer: 3430 errata ID i459 and 3630 errata ID i579
+ *
+ * Note: setting the SAR flag could help for errata ID i478
+ * which applies to 3430 <= ES3.1, but since the SAR feature
+ * is broken, do not use it.
*/
static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
.name = "core_pwrdm",
CHIP_GE_OMAP3630ES1_1),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
+ /*
+ * Setting the SAR flag for errata ID i478 which applies
+ * to 3430 <= ES3.1
+ */
.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
.banks = 2,
.pwrsts_mem_ret = {
#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20)
#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19)
#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18)
+#define OMAP3430_GRPSEL_I2C3_SHIFT 17
#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17)
+#define OMAP3430_GRPSEL_I2C2_SHIFT 16
#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16)
+#define OMAP3430_GRPSEL_I2C1_SHIFT 15
#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15)
#define OMAP3430_GRPSEL_UART2_MASK (1 << 14)
#define OMAP3430_GRPSEL_UART1_MASK (1 << 13)
/*
- * SDRC register values for RX51
+ * SDRC register values for Nokia boards
*
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008, 2010 Nokia Corporation
*
* Lauri Leukkunen <lauri.leukkunen@nokia.com>
*
#include <plat/clock.h>
#include <plat/sdrc.h>
+#include "sdram-nokia.h"
/* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
struct sdram_timings {
u32 tWTR;
};
-static struct omap_sdrc_params rx51_sdrc_params[4];
+static const struct sdram_timings nokia_97dot6mhz_timings[] = {
+ {
+ .casl = 3,
+ .tDAL = 30725,
+ .tDPL = 15362,
+ .tRRD = 10241,
+ .tRCD = 20483,
+ .tRP = 15362,
+ .tRAS = 40967,
+ .tRC = 56330,
+ .tRFC = 138266,
+ .tXSR = 204839,
+
+ .tREF = 7798,
+
+ .tXP = 2,
+ .tCKE = 4,
+ .tWTR = 2,
+ },
+};
-static const struct sdram_timings rx51_timings[] = {
+static const struct sdram_timings nokia_166mhz_timings[] = {
{
.casl = 3,
.tDAL = 33000,
},
};
+static const struct sdram_timings nokia_195dot2mhz_timings[] = {
+ {
+ .casl = 3,
+ .tDAL = 30725,
+ .tDPL = 15362,
+ .tRRD = 10241,
+ .tRCD = 20483,
+ .tRP = 15362,
+ .tRAS = 40967,
+ .tRC = 56330,
+ .tRFC = 138266,
+ .tXSR = 204839,
+
+ .tREF = 7752,
+
+ .tXP = 2,
+ .tCKE = 4,
+ .tWTR = 2,
+ },
+};
+
+static const struct {
+ long rate;
+ struct sdram_timings const *data;
+} nokia_timings[] = {
+ { 83000000, nokia_166mhz_timings },
+ { 97600000, nokia_97dot6mhz_timings },
+ { 166000000, nokia_166mhz_timings },
+ { 195200000, nokia_195dot2mhz_timings },
+};
+static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
+
static unsigned long sdrc_get_fclk_period(long rate)
{
/* In picoseconds */
#ifdef DEBUG
#define SDRC_SET_ONE(reg, st, end, field, rate) \
if (set_sdrc_timing_regval((reg), (st), (end), \
- rx51_timings->field, (rate), #field) < 0) \
+ memory_timings->field, (rate), #field) < 0) \
err = -1;
#else
#define SDRC_SET_ONE(reg, st, end, field, rate) \
if (set_sdrc_timing_regval((reg), (st), (end), \
- rx51_timings->field) < 0) \
+ memory_timings->field) < 0) \
err = -1;
#endif
#ifdef DEBUG
#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
if (set_sdrc_timing_regval_ps((reg), (st), (end), \
- rx51_timings->field, \
+ memory_timings->field, \
(rate), #field) < 0) \
err = -1;
#else
#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
if (set_sdrc_timing_regval_ps((reg), (st), (end), \
- rx51_timings->field, (rate)) < 0) \
+ memory_timings->field, (rate)) < 0) \
err = -1;
#endif
-static int sdrc_timings(int id, long rate)
+static int sdrc_timings(int id, long rate,
+ const struct sdram_timings *memory_timings)
{
u32 ticks_per_ms;
u32 rfr, l;
SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate);
ticks_per_ms = l3_rate;
- rfr = rx51_timings[0].tREF * ticks_per_ms / 1000000;
+ rfr = memory_timings[0].tREF * ticks_per_ms / 1000000;
if (rfr > 65535 + 50)
rfr = 65535;
else
l = rfr << 8;
rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */
- rx51_sdrc_params[id].rate = rate;
- rx51_sdrc_params[id].actim_ctrla = actim_ctrla;
- rx51_sdrc_params[id].actim_ctrlb = actim_ctrlb;
- rx51_sdrc_params[id].rfr_ctrl = rfr_ctrl;
- rx51_sdrc_params[id].mr = 0x32;
+ nokia_sdrc_params[id].rate = rate;
+ nokia_sdrc_params[id].actim_ctrla = actim_ctrla;
+ nokia_sdrc_params[id].actim_ctrlb = actim_ctrlb;
+ nokia_sdrc_params[id].rfr_ctrl = rfr_ctrl;
+ nokia_sdrc_params[id].mr = 0x32;
- rx51_sdrc_params[id + 1].rate = 0;
+ nokia_sdrc_params[id + 1].rate = 0;
return err;
}
-struct omap_sdrc_params *rx51_get_sdram_timings(void)
+struct omap_sdrc_params *nokia_get_sdram_timings(void)
{
- int err;
+ int err = 0;
+ int i;
- err = sdrc_timings(0, 41500000);
- err |= sdrc_timings(1, 83000000);
- err |= sdrc_timings(2, 166000000);
+ for (i = 0; i < ARRAY_SIZE(nokia_timings); i++) {
+ err |= sdrc_timings(i, nokia_timings[i].rate,
+ nokia_timings[i].data);
+ if (err)
+ pr_err("%s: error with rate %ld: %d\n", __func__,
+ nokia_timings[i].rate, err);
+ }
- return &rx51_sdrc_params[0];
+ return err ? NULL : nokia_sdrc_params;
}
--- /dev/null
+/*
+ * SDRC register values for Nokia boards
+ *
+ * Copyright (C) 2010 Nokia
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+struct omap_sdrc_params *nokia_get_sdram_timings(void);
+
static inline void __init omap_uart_reset(struct omap_uart_state *uart)
{
- serial_write_reg(uart, UART_OMAP_MDR1, 0x07);
+ serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
serial_write_reg(uart, UART_OMAP_SCR, 0x08);
- serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
+ serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
}
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
return;
lcr = serial_read_reg(uart, UART_LCR);
- serial_write_reg(uart, UART_LCR, 0xBF);
+ serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
uart->dll = serial_read_reg(uart, UART_DLL);
uart->dlh = serial_read_reg(uart, UART_DLM);
serial_write_reg(uart, UART_LCR, lcr);
uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
uart->wer = serial_read_reg(uart, UART_OMAP_WER);
- serial_write_reg(uart, UART_LCR, 0x80);
+ serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
uart->mcr = serial_read_reg(uart, UART_MCR);
serial_write_reg(uart, UART_LCR, lcr);
uart->context_valid = 0;
if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
- omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
+ omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
else
- serial_write_reg(uart, UART_OMAP_MDR1, 0x7);
- serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+ serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
+
+ serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
efr = serial_read_reg(uart, UART_EFR);
serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
serial_write_reg(uart, UART_IER, 0x0);
- serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+ serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
serial_write_reg(uart, UART_DLL, uart->dll);
serial_write_reg(uart, UART_DLM, uart->dlh);
serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
serial_write_reg(uart, UART_IER, uart->ier);
- serial_write_reg(uart, UART_LCR, 0x80);
+ serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
serial_write_reg(uart, UART_MCR, uart->mcr);
- serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+ serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
serial_write_reg(uart, UART_EFR, efr);
serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
serial_write_reg(uart, UART_OMAP_WER, uart->wer);
serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
+
if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
- omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
+ omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
else
/* UART 16x mode */
- serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
+ serial_write_reg(uart, UART_OMAP_MDR1,
+ UART_OMAP_MDR1_16X_MODE);
}
#else
static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
static void __init omap2_gp_clocksource_init(void)
{
static struct omap_dm_timer *gpt;
- u32 tick_rate, tick_period;
+ u32 tick_rate;
static char err1[] __initdata = KERN_ERR
"%s: failed to request dm-timer\n";
static char err2[] __initdata = KERN_ERR
omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
- tick_period = (tick_rate / HZ) - 1;
omap_dm_timer_set_load_start(gpt, 1, 0);
__iounmap(addr);
}
-#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
-#define __arch_iounmap(a) __arch_iounmap(a)
+#define __arch_ioremap __arch_ioremap
+#define __arch_iounmap __arch_iounmap
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#ifndef __ASSEMBLER__
-#define __arch_ioremap(p, s, t) tegra_ioremap(p, s, t)
-#define __arch_iounmap(v) tegra_iounmap(v)
+#define __arch_ioremap tegra_ioremap
+#define __arch_iounmap tegra_iounmap
void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
void tegra_iounmap(volatile void __iomem *addr);
Say N unless you know you need this.
+config OMAP_IOMMU_IVA2
+ bool
+
choice
prompt "System timer"
default OMAP_32K_TIMER if !ARCH_OMAP15XX
static inline void omap_init_uwire(void) {}
#endif
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
-
-static struct resource wdt_resources[] = {
- {
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device omap_wdt_device = {
- .name = "omap_wdt",
- .id = -1,
- .num_resources = ARRAY_SIZE(wdt_resources),
- .resource = wdt_resources,
-};
-
-static void omap_init_wdt(void)
-{
- if (cpu_is_omap16xx())
- wdt_resources[0].start = 0xfffeb000;
- else if (cpu_is_omap2420())
- wdt_resources[0].start = 0x48022000; /* WDT2 */
- else if (cpu_is_omap2430())
- wdt_resources[0].start = 0x49016000; /* WDT2 */
- else if (cpu_is_omap343x())
- wdt_resources[0].start = 0x48314000; /* WDT2 */
- else if (cpu_is_omap44xx())
- wdt_resources[0].start = 0x4a314000;
- else
- return;
-
- wdt_resources[0].end = wdt_resources[0].start + 0x4f;
-
- (void) platform_device_register(&omap_wdt_device);
-}
-#else
-static inline void omap_init_wdt(void) {}
-#endif
-
#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
static phys_addr_t omap_dsp_phys_mempool_base;
#ifdef CONFIG_ARCH_OMAP15XX
/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
-int omap_dma_in_1510_mode(void)
+static int omap_dma_in_1510_mode(void)
{
return enable_1510_mode;
}
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
#include <mach/hardware.h>
#include <asm/irq.h>
/*
* OMAP1510 GPIO registers
*/
-#define OMAP1510_GPIO_BASE 0xfffce000
#define OMAP1510_GPIO_DATA_INPUT 0x00
#define OMAP1510_GPIO_DATA_OUTPUT 0x04
#define OMAP1510_GPIO_DIR_CONTROL 0x08
/*
* OMAP1610 specific GPIO registers
*/
-#define OMAP1610_GPIO1_BASE 0xfffbe400
-#define OMAP1610_GPIO2_BASE 0xfffbec00
-#define OMAP1610_GPIO3_BASE 0xfffbb400
-#define OMAP1610_GPIO4_BASE 0xfffbbc00
#define OMAP1610_GPIO_REVISION 0x0000
#define OMAP1610_GPIO_SYSCONFIG 0x0010
#define OMAP1610_GPIO_SYSSTATUS 0x0014
/*
* OMAP7XX specific GPIO registers
*/
-#define OMAP7XX_GPIO1_BASE 0xfffbc000
-#define OMAP7XX_GPIO2_BASE 0xfffbc800
-#define OMAP7XX_GPIO3_BASE 0xfffbd000
-#define OMAP7XX_GPIO4_BASE 0xfffbd800
-#define OMAP7XX_GPIO5_BASE 0xfffbe000
-#define OMAP7XX_GPIO6_BASE 0xfffbe800
#define OMAP7XX_GPIO_DATA_INPUT 0x00
#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
#define OMAP7XX_GPIO_DIR_CONTROL 0x08
#define OMAP7XX_GPIO_INT_MASK 0x10
#define OMAP7XX_GPIO_INT_STATUS 0x14
-#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
-
/*
- * omap24xx specific GPIO registers
+ * omap2+ specific GPIO registers
*/
-#define OMAP242X_GPIO1_BASE 0x48018000
-#define OMAP242X_GPIO2_BASE 0x4801a000
-#define OMAP242X_GPIO3_BASE 0x4801c000
-#define OMAP242X_GPIO4_BASE 0x4801e000
-
-#define OMAP243X_GPIO1_BASE 0x4900C000
-#define OMAP243X_GPIO2_BASE 0x4900E000
-#define OMAP243X_GPIO3_BASE 0x49010000
-#define OMAP243X_GPIO4_BASE 0x49012000
-#define OMAP243X_GPIO5_BASE 0x480B6000
-
#define OMAP24XX_GPIO_REVISION 0x0000
-#define OMAP24XX_GPIO_SYSCONFIG 0x0010
-#define OMAP24XX_GPIO_SYSSTATUS 0x0014
#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
#define OMAP24XX_GPIO_IRQENABLE2 0x002c
#define OMAP24XX_GPIO_SETDATAOUT 0x0094
#define OMAP4_GPIO_REVISION 0x0000
-#define OMAP4_GPIO_SYSCONFIG 0x0010
#define OMAP4_GPIO_EOI 0x0020
#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
#define OMAP4_GPIO_IRQWAKEN0 0x0044
#define OMAP4_GPIO_IRQWAKEN1 0x0048
-#define OMAP4_GPIO_SYSSTATUS 0x0114
#define OMAP4_GPIO_IRQENABLE1 0x011c
#define OMAP4_GPIO_WAKE_EN 0x0120
#define OMAP4_GPIO_IRQSTATUS2 0x0128
#define OMAP4_GPIO_SETWKUENA 0x0184
#define OMAP4_GPIO_CLEARDATAOUT 0x0190
#define OMAP4_GPIO_SETDATAOUT 0x0194
-/*
- * omap34xx specific GPIO registers
- */
-
-#define OMAP34XX_GPIO1_BASE 0x48310000
-#define OMAP34XX_GPIO2_BASE 0x49050000
-#define OMAP34XX_GPIO3_BASE 0x49052000
-#define OMAP34XX_GPIO4_BASE 0x49054000
-#define OMAP34XX_GPIO5_BASE 0x49056000
-#define OMAP34XX_GPIO6_BASE 0x49058000
-
-/*
- * OMAP44XX specific GPIO registers
- */
-#define OMAP44XX_GPIO1_BASE 0x4a310000
-#define OMAP44XX_GPIO2_BASE 0x48055000
-#define OMAP44XX_GPIO3_BASE 0x48057000
-#define OMAP44XX_GPIO4_BASE 0x48059000
-#define OMAP44XX_GPIO5_BASE 0x4805B000
-#define OMAP44XX_GPIO6_BASE 0x4805D000
struct gpio_bank {
unsigned long pbase;
u32 suspend_wakeup;
u32 saved_wakeup;
#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
u32 non_wakeup_gpios;
u32 enabled_non_wakeup_gpios;
u32 saved_datain;
u32 saved_fallingdetect;
u32 saved_risingdetect;
-#endif
u32 level_mask;
u32 toggle_mask;
spinlock_t lock;
struct clk *dbck;
u32 mod_usage;
u32 dbck_enable_mask;
+ struct device *dev;
+ bool dbck_flag;
+ int stride;
};
-#define METHOD_MPUIO 0
-#define METHOD_GPIO_1510 1
-#define METHOD_GPIO_1610 2
-#define METHOD_GPIO_7XX 3
-#define METHOD_GPIO_24XX 5
-#define METHOD_GPIO_44XX 6
-
-#ifdef CONFIG_ARCH_OMAP16XX
-static struct gpio_bank gpio_bank_1610[5] = {
- { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
- METHOD_MPUIO },
- { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
- METHOD_GPIO_1610 },
- { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
- METHOD_GPIO_1610 },
- { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
- METHOD_GPIO_1610 },
- { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
- METHOD_GPIO_1610 },
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP15XX
-static struct gpio_bank gpio_bank_1510[2] = {
- { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
- METHOD_MPUIO },
- { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
- METHOD_GPIO_1510 }
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-static struct gpio_bank gpio_bank_7xx[7] = {
- { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
- METHOD_MPUIO },
- { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
- METHOD_GPIO_7XX },
- { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
- METHOD_GPIO_7XX },
- { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
- METHOD_GPIO_7XX },
- { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
- METHOD_GPIO_7XX },
- { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
- METHOD_GPIO_7XX },
- { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
- METHOD_GPIO_7XX },
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2
-
-static struct gpio_bank gpio_bank_242x[4] = {
- { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
- METHOD_GPIO_24XX },
- { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
- METHOD_GPIO_24XX },
- { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
- METHOD_GPIO_24XX },
- { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
- METHOD_GPIO_24XX },
-};
-
-static struct gpio_bank gpio_bank_243x[5] = {
- { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
- METHOD_GPIO_24XX },
- { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
- METHOD_GPIO_24XX },
- { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
- METHOD_GPIO_24XX },
- { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
- METHOD_GPIO_24XX },
- { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
- METHOD_GPIO_24XX },
-};
-
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
-static struct gpio_bank gpio_bank_34xx[6] = {
- { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
- METHOD_GPIO_24XX },
- { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
- METHOD_GPIO_24XX },
- { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
- METHOD_GPIO_24XX },
- { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
- METHOD_GPIO_24XX },
- { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
- METHOD_GPIO_24XX },
- { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
- METHOD_GPIO_24XX },
-};
-
struct omap3_gpio_regs {
- u32 sysconfig;
u32 irqenable1;
u32 irqenable2;
u32 wake_en;
static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
#endif
-#ifdef CONFIG_ARCH_OMAP4
-static struct gpio_bank gpio_bank_44xx[6] = {
- { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
- METHOD_GPIO_44XX },
- { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
- METHOD_GPIO_44XX },
- { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
- METHOD_GPIO_44XX },
- { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
- METHOD_GPIO_44XX },
- { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
- METHOD_GPIO_44XX },
- { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
- METHOD_GPIO_44XX },
-};
+/*
+ * TODO: Cleanup gpio_bank usage as it is having information
+ * related to all instances of the device
+ */
+static struct gpio_bank *gpio_bank;
-#endif
+static int bank_width;
-static struct gpio_bank *gpio_bank;
-static int gpio_bank_count;
+/* TODO: Analyze removing gpio_bank_count usage from driver code */
+int gpio_bank_count;
static inline struct gpio_bank *get_gpio_bank(int gpio)
{
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_IO_CNTL;
+ reg += OMAP_MPUIO_IO_CNTL / bank->stride;
break;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_OUTPUT;
+ reg += OMAP_MPUIO_OUTPUT / bank->stride;
l = __raw_readl(reg);
if (enable)
l |= 1 << gpio;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_INPUT_LATCH;
+ reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
break;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_OUTPUT;
+ reg += OMAP_MPUIO_OUTPUT / bank->stride;
break;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
u32 val;
u32 l;
+ if (!bank->dbck_flag)
+ return;
+
if (debounce < 32)
debounce = 0x01;
else if (debounce > 7936)
l = 1 << get_gpio_index(gpio);
- if (cpu_is_omap44xx())
+ if (bank->method == METHOD_GPIO_44XX)
reg += OMAP4_GPIO_DEBOUNCINGTIME;
else
reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
__raw_writel(debounce, reg);
reg = bank->base;
- if (cpu_is_omap44xx())
+ if (bank->method == METHOD_GPIO_44XX)
reg += OMAP4_GPIO_DEBOUNCENABLE;
else
reg += OMAP24XX_GPIO_DEBOUNCE_EN;
if (debounce) {
val |= l;
- if (cpu_is_omap34xx() || cpu_is_omap44xx())
- clk_enable(bank->dbck);
+ clk_enable(bank->dbck);
} else {
val &= ~l;
- if (cpu_is_omap34xx() || cpu_is_omap44xx())
- clk_disable(bank->dbck);
+ clk_disable(bank->dbck);
}
bank->dbck_enable_mask = val;
switch (bank->method) {
case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_INT_EDGE;
+ reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
break;
#ifdef CONFIG_ARCH_OMAP15XX
case METHOD_GPIO_1510:
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_INT_EDGE;
+ reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
l = __raw_readl(reg);
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
bank->toggle_mask |= 1 << gpio;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_MASKIT;
+ reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
mask = 0xffff;
inv = 1;
break;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_MASKIT;
+ reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
l = __raw_readl(reg);
if (enable)
l &= ~(gpio_mask);
bank = get_irq_data(irq);
#ifdef CONFIG_ARCH_OMAP1
if (bank->method == METHOD_MPUIO)
- isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
+ isr_reg = bank->base +
+ OMAP_MPUIO_GPIO_INT / bank->stride;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (bank->method == METHOD_GPIO_1510)
if (bank->method == METHOD_GPIO_44XX)
isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
#endif
+
+ if (WARN_ON(!isr_reg))
+ goto exit;
+
while(1) {
u32 isr_saved, level_mask = 0;
u32 enabled;
configured, we must unmask the bank interrupt only after
handler(s) are executed in order to avoid spurious bank
interrupt */
+exit:
if (!unmasked)
desc->chip->unmask(irq);
{
struct platform_device *pdev = to_platform_device(dev);
struct gpio_bank *bank = platform_get_drvdata(pdev);
- void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
+ void __iomem *mask_reg = bank->base +
+ OMAP_MPUIO_GPIO_MASKIT / bank->stride;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
{
struct platform_device *pdev = to_platform_device(dev);
struct gpio_bank *bank = platform_get_drvdata(pdev);
- void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
+ void __iomem *mask_reg = bank->base +
+ OMAP_MPUIO_GPIO_MASKIT / bank->stride;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
static inline void mpuio_init(void)
{
- platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
+ struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
+ platform_set_drvdata(&omap_mpuio_device, bank);
if (platform_driver_register(&omap_mpuio_driver) == 0)
(void) platform_device_register(&omap_mpuio_device);
switch (bank->method) {
case METHOD_MPUIO:
- reg += OMAP_MPUIO_IO_CNTL;
+ reg += OMAP_MPUIO_IO_CNTL / bank->stride;
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_DIR_CONTROL;
unsigned long flags;
bank = container_of(chip, struct gpio_bank, chip);
+
+ if (!bank->dbck) {
+ bank->dbck = clk_get(bank->dev, "dbclk");
+ if (IS_ERR(bank->dbck))
+ dev_err(bank->dev, "Could not get gpio dbck\n");
+ }
+
spin_lock_irqsave(&bank->lock, flags);
_set_gpio_debounce(bank, offset, debounce);
spin_unlock_irqrestore(&bank->lock, flags);
/*---------------------------------------------------------------------*/
-static int initialized;
-#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
-static struct clk * gpio_ick;
-#endif
-
-#if defined(CONFIG_ARCH_OMAP2)
-static struct clk * gpio_fck;
-#endif
-
-#if defined(CONFIG_ARCH_OMAP2430)
-static struct clk * gpio5_ick;
-static struct clk * gpio5_fck;
-#endif
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
-#endif
-
-static void __init omap_gpio_show_rev(void)
+static void __init omap_gpio_show_rev(struct gpio_bank *bank)
{
u32 rev;
- if (cpu_is_omap16xx())
- rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
+ if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
+ rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
else if (cpu_is_omap24xx() || cpu_is_omap34xx())
- rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+ rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
else if (cpu_is_omap44xx())
- rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
+ rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
else
return;
*/
static struct lock_class_key gpio_lock_class;
-static int __init _omap_gpio_init(void)
+static inline int init_gpio_info(struct platform_device *pdev)
{
- int i;
- int gpio = 0;
- struct gpio_bank *bank;
- int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
- char clk_name[11];
-
- initialized = 1;
-
-#if defined(CONFIG_ARCH_OMAP1)
- if (cpu_is_omap15xx()) {
- gpio_ick = clk_get(NULL, "arm_gpio_ck");
- if (IS_ERR(gpio_ick))
- printk("Could not get arm_gpio_ck\n");
- else
- clk_enable(gpio_ick);
+ /* TODO: Analyze removing gpio_bank_count usage from driver code */
+ gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
+ GFP_KERNEL);
+ if (!gpio_bank) {
+ dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
+ return -ENOMEM;
}
-#endif
-#if defined(CONFIG_ARCH_OMAP2)
- if (cpu_class_is_omap2()) {
- gpio_ick = clk_get(NULL, "gpios_ick");
- if (IS_ERR(gpio_ick))
- printk("Could not get gpios_ick\n");
- else
- clk_enable(gpio_ick);
- gpio_fck = clk_get(NULL, "gpios_fck");
- if (IS_ERR(gpio_fck))
- printk("Could not get gpios_fck\n");
- else
- clk_enable(gpio_fck);
+ return 0;
+}
- /*
- * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
- */
-#if defined(CONFIG_ARCH_OMAP2430)
- if (cpu_is_omap2430()) {
- gpio5_ick = clk_get(NULL, "gpio5_ick");
- if (IS_ERR(gpio5_ick))
- printk("Could not get gpio5_ick\n");
- else
- clk_enable(gpio5_ick);
- gpio5_fck = clk_get(NULL, "gpio5_fck");
- if (IS_ERR(gpio5_fck))
- printk("Could not get gpio5_fck\n");
- else
- clk_enable(gpio5_fck);
+/* TODO: Cleanup cpu_is_* checks */
+static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
+{
+ if (cpu_class_is_omap2()) {
+ if (cpu_is_omap44xx()) {
+ __raw_writel(0xffffffff, bank->base +
+ OMAP4_GPIO_IRQSTATUSCLR0);
+ __raw_writel(0x00000000, bank->base +
+ OMAP4_GPIO_DEBOUNCENABLE);
+ /* Initialize interface clk ungated, module enabled */
+ __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
+ } else if (cpu_is_omap34xx()) {
+ __raw_writel(0x00000000, bank->base +
+ OMAP24XX_GPIO_IRQENABLE1);
+ __raw_writel(0xffffffff, bank->base +
+ OMAP24XX_GPIO_IRQSTATUS1);
+ __raw_writel(0x00000000, bank->base +
+ OMAP24XX_GPIO_DEBOUNCE_EN);
+
+ /* Initialize interface clk ungated, module enabled */
+ __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
+ } else if (cpu_is_omap24xx()) {
+ static const u32 non_wakeup_gpios[] = {
+ 0xe203ffc0, 0x08700040
+ };
+ if (id < ARRAY_SIZE(non_wakeup_gpios))
+ bank->non_wakeup_gpios = non_wakeup_gpios[id];
}
-#endif
- }
-#endif
+ } else if (cpu_class_is_omap1()) {
+ if (bank_is_mpuio(bank))
+ __raw_writew(0xffff, bank->base +
+ OMAP_MPUIO_GPIO_MASKIT / bank->stride);
+ if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
+ __raw_writew(0xffff, bank->base
+ + OMAP1510_GPIO_INT_MASK);
+ __raw_writew(0x0000, bank->base
+ + OMAP1510_GPIO_INT_STATUS);
+ }
+ if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
+ __raw_writew(0x0000, bank->base
+ + OMAP1610_GPIO_IRQENABLE1);
+ __raw_writew(0xffff, bank->base
+ + OMAP1610_GPIO_IRQSTATUS1);
+ __raw_writew(0x0014, bank->base
+ + OMAP1610_GPIO_SYSCONFIG);
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
- if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
- sprintf(clk_name, "gpio%d_ick", i + 1);
- gpio_iclks[i] = clk_get(NULL, clk_name);
- if (IS_ERR(gpio_iclks[i]))
- printk(KERN_ERR "Could not get %s\n", clk_name);
- else
- clk_enable(gpio_iclks[i]);
+ /*
+ * Enable system clock for GPIO module.
+ * The CAM_CLK_CTRL *is* really the right place.
+ */
+ omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
+ ULPD_CAM_CLK_CTRL);
+ }
+ if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
+ __raw_writel(0xffffffff, bank->base
+ + OMAP7XX_GPIO_INT_MASK);
+ __raw_writel(0x00000000, bank->base
+ + OMAP7XX_GPIO_INT_STATUS);
}
}
-#endif
+}
+static void __init omap_gpio_chip_init(struct gpio_bank *bank)
+{
+ int j;
+ static int gpio;
-#ifdef CONFIG_ARCH_OMAP15XX
- if (cpu_is_omap15xx()) {
- gpio_bank_count = 2;
- gpio_bank = gpio_bank_1510;
- bank_size = SZ_2K;
- }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
- if (cpu_is_omap16xx()) {
- gpio_bank_count = 5;
- gpio_bank = gpio_bank_1610;
- bank_size = SZ_2K;
- }
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
- if (cpu_is_omap7xx()) {
- gpio_bank_count = 7;
- gpio_bank = gpio_bank_7xx;
- bank_size = SZ_2K;
- }
-#endif
-#ifdef CONFIG_ARCH_OMAP2
- if (cpu_is_omap242x()) {
- gpio_bank_count = 4;
- gpio_bank = gpio_bank_242x;
- }
- if (cpu_is_omap243x()) {
- gpio_bank_count = 5;
- gpio_bank = gpio_bank_243x;
- }
+ bank->mod_usage = 0;
+ /*
+ * REVISIT eventually switch from OMAP-specific gpio structs
+ * over to the generic ones
+ */
+ bank->chip.request = omap_gpio_request;
+ bank->chip.free = omap_gpio_free;
+ bank->chip.direction_input = gpio_input;
+ bank->chip.get = gpio_get;
+ bank->chip.direction_output = gpio_output;
+ bank->chip.set_debounce = gpio_debounce;
+ bank->chip.set = gpio_set;
+ bank->chip.to_irq = gpio_2irq;
+ if (bank_is_mpuio(bank)) {
+ bank->chip.label = "mpuio";
+#ifdef CONFIG_ARCH_OMAP16XX
+ bank->chip.dev = &omap_mpuio_device.dev;
#endif
-#ifdef CONFIG_ARCH_OMAP3
- if (cpu_is_omap34xx()) {
- gpio_bank_count = OMAP34XX_NR_GPIOS;
- gpio_bank = gpio_bank_34xx;
+ bank->chip.base = OMAP_MPUIO(0);
+ } else {
+ bank->chip.label = "gpio";
+ bank->chip.base = gpio;
+ gpio += bank_width;
}
-#endif
-#ifdef CONFIG_ARCH_OMAP4
- if (cpu_is_omap44xx()) {
- gpio_bank_count = OMAP34XX_NR_GPIOS;
- gpio_bank = gpio_bank_44xx;
+ bank->chip.ngpio = bank_width;
+
+ gpiochip_add(&bank->chip);
+
+ for (j = bank->virtual_irq_start;
+ j < bank->virtual_irq_start + bank_width; j++) {
+ lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
+ set_irq_chip_data(j, bank);
+ if (bank_is_mpuio(bank))
+ set_irq_chip(j, &mpuio_irq_chip);
+ else
+ set_irq_chip(j, &gpio_irq_chip);
+ set_irq_handler(j, handle_simple_irq);
+ set_irq_flags(j, IRQF_VALID);
}
-#endif
- for (i = 0; i < gpio_bank_count; i++) {
- int j, gpio_count = 16;
+ set_irq_chained_handler(bank->irq, gpio_irq_handler);
+ set_irq_data(bank->irq, bank);
+}
+
+static int __devinit omap_gpio_probe(struct platform_device *pdev)
+{
+ static int gpio_init_done;
+ struct omap_gpio_platform_data *pdata;
+ struct resource *res;
+ int id;
+ struct gpio_bank *bank;
- bank = &gpio_bank[i];
- spin_lock_init(&bank->lock);
+ if (!pdev->dev.platform_data)
+ return -EINVAL;
- /* Static mapping, never released */
- bank->base = ioremap(bank->pbase, bank_size);
- if (!bank->base) {
- printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
- continue;
- }
+ pdata = pdev->dev.platform_data;
- if (bank_is_mpuio(bank))
- __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
- if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
- __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
- __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
- }
- if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
- __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
- __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
- __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
- }
- if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
- __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
- __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
+ if (!gpio_init_done) {
+ int ret;
- gpio_count = 32; /* 7xx has 32-bit GPIOs */
- }
+ ret = init_gpio_info(pdev);
+ if (ret)
+ return ret;
+ }
-#ifdef CONFIG_ARCH_OMAP2PLUS
- if ((bank->method == METHOD_GPIO_24XX) ||
- (bank->method == METHOD_GPIO_44XX)) {
- static const u32 non_wakeup_gpios[] = {
- 0xe203ffc0, 0x08700040
- };
+ id = pdev->id;
+ bank = &gpio_bank[id];
- if (cpu_is_omap44xx()) {
- __raw_writel(0xffffffff, bank->base +
- OMAP4_GPIO_IRQSTATUSCLR0);
- __raw_writew(0x0015, bank->base +
- OMAP4_GPIO_SYSCONFIG);
- __raw_writel(0x00000000, bank->base +
- OMAP4_GPIO_DEBOUNCENABLE);
- /*
- * Initialize interface clock ungated,
- * module enabled
- */
- __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
- } else {
- __raw_writel(0x00000000, bank->base +
- OMAP24XX_GPIO_IRQENABLE1);
- __raw_writel(0xffffffff, bank->base +
- OMAP24XX_GPIO_IRQSTATUS1);
- __raw_writew(0x0015, bank->base +
- OMAP24XX_GPIO_SYSCONFIG);
- __raw_writel(0x00000000, bank->base +
- OMAP24XX_GPIO_DEBOUNCE_EN);
-
- /*
- * Initialize interface clock ungated,
- * module enabled
- */
- __raw_writel(0, bank->base +
- OMAP24XX_GPIO_CTRL);
- }
- if (cpu_is_omap24xx() &&
- i < ARRAY_SIZE(non_wakeup_gpios))
- bank->non_wakeup_gpios = non_wakeup_gpios[i];
- gpio_count = 32;
- }
-#endif
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (unlikely(!res)) {
+ dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
+ return -ENODEV;
+ }
- bank->mod_usage = 0;
- /* REVISIT eventually switch from OMAP-specific gpio structs
- * over to the generic ones
- */
- bank->chip.request = omap_gpio_request;
- bank->chip.free = omap_gpio_free;
- bank->chip.direction_input = gpio_input;
- bank->chip.get = gpio_get;
- bank->chip.direction_output = gpio_output;
- bank->chip.set_debounce = gpio_debounce;
- bank->chip.set = gpio_set;
- bank->chip.to_irq = gpio_2irq;
- if (bank_is_mpuio(bank)) {
- bank->chip.label = "mpuio";
-#ifdef CONFIG_ARCH_OMAP16XX
- bank->chip.dev = &omap_mpuio_device.dev;
-#endif
- bank->chip.base = OMAP_MPUIO(0);
- } else {
- bank->chip.label = "gpio";
- bank->chip.base = gpio;
- gpio += gpio_count;
- }
- bank->chip.ngpio = gpio_count;
+ bank->irq = res->start;
+ bank->virtual_irq_start = pdata->virtual_irq_start;
+ bank->method = pdata->bank_type;
+ bank->dev = &pdev->dev;
+ bank->dbck_flag = pdata->dbck_flag;
+ bank->stride = pdata->bank_stride;
+ bank_width = pdata->bank_width;
- gpiochip_add(&bank->chip);
+ spin_lock_init(&bank->lock);
- for (j = bank->virtual_irq_start;
- j < bank->virtual_irq_start + gpio_count; j++) {
- lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
- set_irq_chip_data(j, bank);
- if (bank_is_mpuio(bank))
- set_irq_chip(j, &mpuio_irq_chip);
- else
- set_irq_chip(j, &gpio_irq_chip);
- set_irq_handler(j, handle_simple_irq);
- set_irq_flags(j, IRQF_VALID);
- }
- set_irq_chained_handler(bank->irq, gpio_irq_handler);
- set_irq_data(bank->irq, bank);
-
- if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- sprintf(clk_name, "gpio%d_dbck", i + 1);
- bank->dbck = clk_get(NULL, clk_name);
- if (IS_ERR(bank->dbck))
- printk(KERN_ERR "Could not get %s\n", clk_name);
- }
+ /* Static mapping, never released */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (unlikely(!res)) {
+ dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
+ return -ENODEV;
}
- /* Enable system clock for GPIO module.
- * The CAM_CLK_CTRL *is* really the right place. */
- if (cpu_is_omap16xx())
- omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
+ bank->base = ioremap(res->start, resource_size(res));
+ if (!bank->base) {
+ dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
+ return -ENOMEM;
+ }
- /* Enable autoidle for the OCP interface */
- if (cpu_is_omap24xx())
- omap_writel(1 << 0, 0x48019010);
- if (cpu_is_omap34xx())
- omap_writel(1 << 0, 0x48306814);
+ pm_runtime_enable(bank->dev);
+ pm_runtime_get_sync(bank->dev);
+
+ omap_gpio_mod_init(bank, id);
+ omap_gpio_chip_init(bank);
+ omap_gpio_show_rev(bank);
- omap_gpio_show_rev();
+ if (!gpio_init_done)
+ gpio_init_done = 1;
return 0;
}
/* saving banks from 2-6 only since GPIO1 is in WKUP */
for (i = 1; i < gpio_bank_count; i++) {
struct gpio_bank *bank = &gpio_bank[i];
- gpio_context[i].sysconfig =
- __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
gpio_context[i].irqenable1 =
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
gpio_context[i].irqenable2 =
for (i = 1; i < gpio_bank_count; i++) {
struct gpio_bank *bank = &gpio_bank[i];
- __raw_writel(gpio_context[i].sysconfig,
- bank->base + OMAP24XX_GPIO_SYSCONFIG);
__raw_writel(gpio_context[i].irqenable1,
bank->base + OMAP24XX_GPIO_IRQENABLE1);
__raw_writel(gpio_context[i].irqenable2,
}
#endif
+static struct platform_driver omap_gpio_driver = {
+ .probe = omap_gpio_probe,
+ .driver = {
+ .name = "omap_gpio",
+ },
+};
+
/*
- * This may get called early from board specific init
- * for boards that have interrupts routed via FPGA.
+ * gpio driver register needs to be done before
+ * machine_init functions access gpio APIs.
+ * Hence omap_gpio_drv_reg() is a postcore_initcall.
*/
-int __init omap_gpio_init(void)
+static int __init omap_gpio_drv_reg(void)
{
- if (!initialized)
- return _omap_gpio_init();
- else
- return 0;
+ return platform_driver_register(&omap_gpio_driver);
}
+postcore_initcall(omap_gpio_drv_reg);
static int __init omap_gpio_sysinit(void)
{
int ret = 0;
- if (!initialized)
- ret = _omap_gpio_init();
-
mpuio_init();
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c-omap.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/clk.h>
#include <mach/irqs.h>
#include <plat/mux.h>
#include <plat/i2c.h>
#include <plat/omap-pm.h>
+#include <plat/omap_device.h>
#define OMAP_I2C_SIZE 0x3f
#define OMAP1_I2C_BASE 0xfffb3800
-#define OMAP2_I2C_BASE1 0x48070000
-#define OMAP2_I2C_BASE2 0x48072000
-#define OMAP2_I2C_BASE3 0x48060000
-#define OMAP4_I2C_BASE4 0x48350000
-static const char name[] = "i2c_omap";
+static const char name[] = "omap_i2c";
#define I2C_RESOURCE_BUILDER(base, irq) \
{ \
static struct resource i2c_resources[][2] = {
{ I2C_RESOURCE_BUILDER(0, 0) },
-#if defined(CONFIG_ARCH_OMAP2PLUS)
- { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) },
-#endif
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
- { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) },
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
- { I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) },
-#endif
};
#define I2C_DEV_BUILDER(bus_id, res, data) \
}, \
}
-static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
+#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16
+#define OMAP_I2C_MAX_CONTROLLERS 4
+static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
static struct platform_device omap_i2c_devices[] = {
I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
-#if defined(CONFIG_ARCH_OMAP2PLUS)
- I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
-#endif
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
- I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
- I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]),
-#endif
};
#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
return ports;
}
-/* Shared between omap2 and 3 */
-static resource_size_t omap2_i2c_irq[3] __initdata = {
- INT_24XX_I2C1_IRQ,
- INT_24XX_I2C2_IRQ,
- INT_34XX_I2C3_IRQ,
-};
-
-static resource_size_t omap4_i2c_irq[4] __initdata = {
- OMAP44XX_IRQ_I2C1,
- OMAP44XX_IRQ_I2C2,
- OMAP44XX_IRQ_I2C3,
- OMAP44XX_IRQ_I2C4,
-};
-
-static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
+static inline int omap1_i2c_add_bus(int bus_id)
{
- struct omap_i2c_bus_platform_data *pd;
+ struct platform_device *pdev;
+ struct omap_i2c_bus_platform_data *pdata;
struct resource *res;
- pd = pdev->dev.platform_data;
+ omap1_i2c_mux_pins(bus_id);
+
+ pdev = &omap_i2c_devices[bus_id - 1];
res = pdev->resource;
res[0].start = OMAP1_I2C_BASE;
res[0].end = res[0].start + OMAP_I2C_SIZE;
res[1].start = INT_I2C;
- omap1_i2c_mux_pins(bus_id);
+ pdata = &i2c_pdata[bus_id - 1];
return platform_device_register(pdev);
}
+
/*
* XXX This function is a temporary compatibility wrapper - only
* needed until the I2C driver can be converted to call
omap_pm_set_max_mpu_wakeup_lat(dev, t);
}
-static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
-{
- struct resource *res;
- resource_size_t *irq;
+static struct omap_device_pm_latency omap_i2c_latency[] = {
+ [0] = {
+ .deactivate_func = omap_device_idle_hwmods,
+ .activate_func = omap_device_enable_hwmods,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+ },
+};
- res = pdev->resource;
+#ifdef CONFIG_ARCH_OMAP2PLUS
+static inline int omap2_i2c_add_bus(int bus_id)
+{
+ int l;
+ struct omap_hwmod *oh;
+ struct omap_device *od;
+ char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
+ struct omap_i2c_bus_platform_data *pdata;
- if (!cpu_is_omap44xx())
- irq = omap2_i2c_irq;
- else
- irq = omap4_i2c_irq;
+ omap2_i2c_mux_pins(bus_id);
- if (bus_id == 1) {
- res[0].start = OMAP2_I2C_BASE1;
- res[0].end = res[0].start + OMAP_I2C_SIZE;
+ l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
+ WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
+ "String buffer overflow in I2C%d device setup\n", bus_id);
+ oh = omap_hwmod_lookup(oh_name);
+ if (!oh) {
+ pr_err("Could not look up %s\n", oh_name);
+ return -EEXIST;
}
- res[1].start = irq[bus_id - 1];
- omap2_i2c_mux_pins(bus_id);
-
+ pdata = &i2c_pdata[bus_id - 1];
/*
* When waiting for completion of a i2c transfer, we need to
* set a wake up latency constraint for the MPU. This is to
* ensure quick enough wakeup from idle, when transfer
* completes.
+ * Only omap3 has support for constraints
*/
- if (cpu_is_omap34xx()) {
- struct omap_i2c_bus_platform_data *pd;
-
- pd = pdev->dev.platform_data;
- pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
- }
-
- return platform_device_register(pdev);
+ if (cpu_is_omap34xx())
+ pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
+ od = omap_device_build(name, bus_id, oh, pdata,
+ sizeof(struct omap_i2c_bus_platform_data),
+ omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0);
+ WARN(IS_ERR(od), "Could not build omap_device for %s\n", name);
+
+ return PTR_ERR(od);
}
+#else
+static inline int omap2_i2c_add_bus(int bus_id)
+{
+ return 0;
+}
+#endif
static int __init omap_i2c_add_bus(int bus_id)
{
- struct platform_device *pdev;
-
- pdev = &omap_i2c_devices[bus_id - 1];
-
if (cpu_class_is_omap1())
- return omap1_i2c_add_bus(pdev, bus_id);
+ return omap1_i2c_add_bus(bus_id);
else
- return omap2_i2c_add_bus(pdev, bus_id);
+ return omap2_i2c_add_bus(bus_id);
}
/**
#ifndef __ASM_ARCH_OMAP_FPGA_H
#define __ASM_ARCH_OMAP_FPGA_H
-#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
extern void omap1510_fpga_init_irq(void);
-#else
-#define omap1510_fpga_init_irq() (0)
-#endif
#define fpga_read(reg) __raw_readb(reg)
#define fpga_write(val, reg) __raw_writeb(val, reg)
#define __ASM_ARCH_OMAP_GPIO_H
#include <linux/io.h>
+#include <linux/platform_device.h>
#include <mach/irqs.h>
#define OMAP1_MPUIO_BASE 0xfffb5000
-#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
-
-#define OMAP_MPUIO_INPUT_LATCH 0x00
-#define OMAP_MPUIO_OUTPUT 0x02
-#define OMAP_MPUIO_IO_CNTL 0x04
-#define OMAP_MPUIO_KBR_LATCH 0x08
-#define OMAP_MPUIO_KBC 0x0a
-#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
-#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
-#define OMAP_MPUIO_KBD_INT 0x10
-#define OMAP_MPUIO_GPIO_INT 0x12
-#define OMAP_MPUIO_KBD_MASKIT 0x14
-#define OMAP_MPUIO_GPIO_MASKIT 0x16
-#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
-#define OMAP_MPUIO_LATCH 0x1a
-#else
+/*
+ * These are the omap15xx/16xx offsets. The omap7xx offset are
+ * OMAP_MPUIO_ / 2 offsets below.
+ */
#define OMAP_MPUIO_INPUT_LATCH 0x00
#define OMAP_MPUIO_OUTPUT 0x04
#define OMAP_MPUIO_IO_CNTL 0x08
#define OMAP_MPUIO_GPIO_MASKIT 0x2c
#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
#define OMAP_MPUIO_LATCH 0x34
-#endif
#define OMAP34XX_NR_GPIOS 6
IH_MPUIO_BASE + ((nr) & 0x0f) : \
IH_GPIO_BASE + (nr))
-extern int omap_gpio_init(void); /* Call from board init only */
+#define METHOD_MPUIO 0
+#define METHOD_GPIO_1510 1
+#define METHOD_GPIO_1610 2
+#define METHOD_GPIO_7XX 3
+#define METHOD_GPIO_24XX 5
+#define METHOD_GPIO_44XX 6
+
+struct omap_gpio_dev_attr {
+ int bank_width; /* GPIO bank width */
+ bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
+};
+
+struct omap_gpio_platform_data {
+ u16 virtual_irq_start;
+ int bank_type;
+ int bank_width; /* GPIO bank width */
+ int bank_stride; /* Only needed for omap1 MPUIO */
+ bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
+};
+
+/* TODO: Analyze removing gpio_bank_count usage from driver code */
+extern int gpio_bank_count;
+
extern void omap2_gpio_prepare_for_idle(int power_state);
extern void omap2_gpio_resume_after_idle(void);
extern void omap_set_gpio_debounce(int gpio, int enable);
}
#endif
+/**
+ * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
+ * @fifo_depth: total controller FIFO size (in bytes)
+ * @flags: differences in hardware support capability
+ *
+ * @fifo_depth represents what exists on the hardware, not what is
+ * actually configured at runtime by the device driver.
+ */
+struct omap_i2c_dev_attr {
+ u8 fifo_depth;
+ u8 flags;
+};
+
void __init omap1_i2c_mux_pins(int bus_id);
void __init omap2_i2c_mux_pins(int bus_id);
extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1);
-#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
-#define __arch_iounmap(v) omap_iounmap(v)
+#define __arch_ioremap omap_ioremap
+#define __arch_iounmap omap_iounmap
void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
void omap_iounmap(volatile void __iomem *addr);
int (*isr)(struct iommu *obj);
void *ctx; /* iommu context: registres saved area */
+ u32 da_start;
+ u32 da_end;
};
struct cr_regs {
const char *name;
const char *clk_name;
const int nr_tlb_entries;
+ u32 da_start;
+ u32 da_end;
};
#if defined(CONFIG_ARCH_OMAP1)
extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
+extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
extern struct iommu *iommu_get(const char *name);
extern void iommu_put(struct iommu *obj);
/*
* OMAP-1610 specific IRQ numbers for interrupt handler 1
*/
-#define INT_1610_IH2_IRQ 0
+#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ
#define INT_1610_IH2_FIQ 2
#define INT_1610_McBSP2_TX 4
#define INT_1610_McBSP2_RX 5
--- /dev/null
+/*
+ * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+
+/* L4 CORE */
+#define OMAP3_L4_CORE_FW_I2C1_REGION 21
+#define OMAP3_L4_CORE_FW_I2C1_TA_REGION 22
+#define OMAP3_L4_CORE_FW_I2C2_REGION 23
+#define OMAP3_L4_CORE_FW_I2C2_TA_REGION 24
+#define OMAP3_L4_CORE_FW_I2C3_REGION 73
+#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74
+
+#endif
struct kfifo fifo;
struct work_struct work;
struct tasklet_struct tasklet;
- int (*callback)(void *);
struct omap_mbox *mbox;
+ bool full;
};
struct omap_mbox {
struct omap_mbox_ops *ops;
struct device *dev;
void *priv;
+ int use_count;
+ struct blocking_notifier_head notifier;
};
int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
void omap_mbox_init_seq(struct omap_mbox *);
-struct omap_mbox *omap_mbox_get(const char *);
-void omap_mbox_put(struct omap_mbox *);
+struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb);
+void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb);
int omap_mbox_register(struct device *parent, struct omap_mbox **);
int omap_mbox_unregister(void);
#include <plat/mux.h>
-#define DRIVER_NAME "omap-hsuart"
+#define DRIVER_NAME "omap_uart"
/*
* Use tty device name as ttyO, [O -> OMAP]
*/
#define OMAP_SERIAL_NAME "ttyO"
-#define OMAP_MDR1_DISABLE 0x07
-#define OMAP_MDR1_MODE13X 0x03
-#define OMAP_MDR1_MODE16X 0x00
#define OMAP_MODE13X_SPEED 230400
-/*
- * LCR = 0XBF: Switch to Configuration Mode B.
- * In configuration mode b allow access
- * to EFR,DLL,DLH.
- * Reference OMAP TRM Chapter 17
- * Section: 1.4.3 Mode Selection
- */
-#define OMAP_UART_LCR_CONF_MDB 0XBF
-
/* WER = 0x7F
* Enable module level wakeup in WER reg
*/
/* omap3 based boards using UART3 */
DEBUG_LL_OMAP3(3, cm_t35);
DEBUG_LL_OMAP3(3, cm_t3517);
+ DEBUG_LL_OMAP3(3, craneboard);
DEBUG_LL_OMAP3(3, igep0020);
DEBUG_LL_OMAP3(3, igep0030);
+ DEBUG_LL_OMAP3(3, nokia_rm680);
DEBUG_LL_OMAP3(3, nokia_rx51);
DEBUG_LL_OMAP3(3, omap3517evm);
DEBUG_LL_OMAP3(3, omap3_beagle);
__iounmap(addr);
}
EXPORT_SYMBOL(omap_iounmap);
-
-/*
- * NOTE: Please use ioremap + __raw_read/write where possible instead of these
- */
-
-u8 omap_readb(u32 pa)
-{
- if (cpu_class_is_omap1())
- return __raw_readb(OMAP1_IO_ADDRESS(pa));
- else
- return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readb);
-
-u16 omap_readw(u32 pa)
-{
- if (cpu_class_is_omap1())
- return __raw_readw(OMAP1_IO_ADDRESS(pa));
- else
- return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readw);
-
-u32 omap_readl(u32 pa)
-{
- if (cpu_class_is_omap1())
- return __raw_readl(OMAP1_IO_ADDRESS(pa));
- else
- return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readl);
-
-void omap_writeb(u8 v, u32 pa)
-{
- if (cpu_class_is_omap1())
- __raw_writeb(v, OMAP1_IO_ADDRESS(pa));
- else
- __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writeb);
-
-void omap_writew(u16 v, u32 pa)
-{
- if (cpu_class_is_omap1())
- __raw_writew(v, OMAP1_IO_ADDRESS(pa));
- else
- __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writew);
-
-void omap_writel(u32 v, u32 pa)
-{
- if (cpu_class_is_omap1())
- __raw_writel(v, OMAP1_IO_ADDRESS(pa));
- else
- __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writel);
return strcmp(obj->name, name) == 0;
}
+/**
+ * iommu_set_da_range - Set a valid device address range
+ * @obj: target iommu
+ * @start Start of valid range
+ * @end End of valid range
+ **/
+int iommu_set_da_range(struct iommu *obj, u32 start, u32 end)
+{
+
+ if (!obj)
+ return -EFAULT;
+
+ if (end < start || !PAGE_ALIGN(start | end))
+ return -EINVAL;
+
+ obj->da_start = start;
+ obj->da_end = end;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(iommu_set_da_range);
+
/**
* iommu_get - Get iommu handler
* @name: target iommu name
obj->name = pdata->name;
obj->dev = &pdev->dev;
obj->ctx = (void *)obj + sizeof(*obj);
+ obj->da_start = pdata->da_start;
+ obj->da_end = pdata->da_end;
mutex_init(&obj->iommu_lock);
mutex_init(&obj->mmap_lock);
}
#define sgtable_ok(x) (!!sgtable_len(x))
+static unsigned max_alignment(u32 addr)
+{
+ int i;
+ unsigned pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, };
+ for (i = 0; i < ARRAY_SIZE(pagesize) && addr & (pagesize[i] - 1); i++)
+ ;
+ return (i < ARRAY_SIZE(pagesize)) ? pagesize[i] : 0;
+}
+
/*
* calculate the optimal number sg elements from total bytes based on
* iommu superpages
*/
-static unsigned int sgtable_nents(size_t bytes)
+static unsigned sgtable_nents(size_t bytes, u32 da, u32 pa)
{
- int i;
- unsigned int nr_entries;
- const unsigned long pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, };
+ unsigned nr_entries = 0, ent_sz;
if (!IS_ALIGNED(bytes, PAGE_SIZE)) {
pr_err("%s: wrong size %08x\n", __func__, bytes);
return 0;
}
- nr_entries = 0;
- for (i = 0; i < ARRAY_SIZE(pagesize); i++) {
- if (bytes >= pagesize[i]) {
- nr_entries += (bytes / pagesize[i]);
- bytes %= pagesize[i];
- }
+ while (bytes) {
+ ent_sz = max_alignment(da | pa);
+ ent_sz = min_t(unsigned, ent_sz, iopgsz_max(bytes));
+ nr_entries++;
+ da += ent_sz;
+ pa += ent_sz;
+ bytes -= ent_sz;
}
- BUG_ON(bytes);
return nr_entries;
}
/* allocate and initialize sg_table header(a kind of 'superblock') */
-static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags)
+static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags,
+ u32 da, u32 pa)
{
unsigned int nr_entries;
int err;
if (!IS_ALIGNED(bytes, PAGE_SIZE))
return ERR_PTR(-EINVAL);
- /* FIXME: IOVMF_DA_FIXED should support 'superpages' */
- if ((flags & IOVMF_LINEAR) && (flags & IOVMF_DA_ANON)) {
- nr_entries = sgtable_nents(bytes);
+ if (flags & IOVMF_LINEAR) {
+ nr_entries = sgtable_nents(bytes, da, pa);
if (!nr_entries)
return ERR_PTR(-EINVAL);
} else
alignement = PAGE_SIZE;
if (flags & IOVMF_DA_ANON) {
- /*
- * Reserve the first page for NULL
- */
- start = PAGE_SIZE;
+ start = obj->da_start;
+
if (flags & IOVMF_LINEAR)
alignement = iopgsz_max(bytes);
start = roundup(start, alignement);
+ } else if (start < obj->da_start || start > obj->da_end ||
+ obj->da_end - start < bytes) {
+ return ERR_PTR(-EINVAL);
}
tmp = NULL;
prev_end = 0;
list_for_each_entry(tmp, &obj->mmap, list) {
- if (prev_end >= start)
+ if (prev_end > start)
break;
- if (start + bytes < tmp->da_start)
+ if (tmp->da_start > start && (tmp->da_start - start) >= bytes)
goto found;
- if (flags & IOVMF_DA_ANON)
+ if (tmp->da_end >= start && flags & IOVMF_DA_ANON)
start = roundup(tmp->da_end + 1, alignement);
prev_end = tmp->da_end;
}
- if ((start > prev_end) && (ULONG_MAX - start >= bytes))
+ if ((start >= prev_end) && (obj->da_end - start >= bytes))
goto found;
dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n",
BUG_ON(!sgt);
}
-static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
+static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, u32 da,
+ size_t len)
{
unsigned int i;
struct scatterlist *sg;
va = phys_to_virt(pa);
for_each_sg(sgt->sgl, sg, sgt->nents, i) {
- size_t bytes;
+ unsigned bytes;
- bytes = iopgsz_max(len);
+ bytes = max_alignment(da | pa);
+ bytes = min_t(unsigned, bytes, iopgsz_max(len));
BUG_ON(!iopgsz_ok(bytes));
* 'pa' is cotinuous(linear).
*/
pa += bytes;
+ da += bytes;
len -= bytes;
}
BUG_ON(len);
if (!va)
return -ENOMEM;
- sgt = sgtable_alloc(bytes, flags);
+ flags &= IOVMF_HW_MASK;
+ flags |= IOVMF_DISCONT;
+ flags |= IOVMF_ALLOC;
+ flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
+
+ sgt = sgtable_alloc(bytes, flags, da, 0);
if (IS_ERR(sgt)) {
da = PTR_ERR(sgt);
goto err_sgt_alloc;
}
sgtable_fill_vmalloc(sgt, va);
- flags &= IOVMF_HW_MASK;
- flags |= IOVMF_DISCONT;
- flags |= IOVMF_ALLOC;
- flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
-
da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
if (IS_ERR_VALUE(da))
goto err_iommu_vmap;
{
struct sg_table *sgt;
- sgt = sgtable_alloc(bytes, flags);
+ sgt = sgtable_alloc(bytes, flags, da, pa);
if (IS_ERR(sgt))
return PTR_ERR(sgt);
- sgtable_fill_kmalloc(sgt, pa, bytes);
+ sgtable_fill_kmalloc(sgt, pa, da, bytes);
da = map_iommu_region(obj, da, sgt, va, bytes, flags);
if (IS_ERR_VALUE(da)) {
struct sg_table *sgt;
typedef void (*func_t)(const void *);
- sgt = unmap_vm_area(obj, da, (func_t)__iounmap,
+ sgt = unmap_vm_area(obj, da, (func_t)iounmap,
IOVMF_LINEAR | IOVMF_MMIO);
if (!sgt)
dev_dbg(obj->dev, "%s: No sgt\n", __func__);
#include <linux/slab.h>
#include <linux/kfifo.h>
#include <linux/err.h>
+#include <linux/notifier.h>
#include <plat/mailbox.h>
static struct workqueue_struct *mboxd;
static struct omap_mbox **mboxes;
-static bool rq_full;
static int mbox_configured;
static DEFINE_MUTEX(mbox_configured_lock);
struct omap_mbox_queue *mq = mbox->txq;
int ret = 0, len;
- spin_lock(&mq->lock);
+ spin_lock_bh(&mq->lock);
if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
ret = -ENOMEM;
goto out;
}
+ if (kfifo_is_empty(&mq->fifo) && !__mbox_poll_for_space(mbox)) {
+ mbox_fifo_write(mbox, msg);
+ goto out;
+ }
+
len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
WARN_ON(len != sizeof(msg));
tasklet_schedule(&mbox->txq->tasklet);
out:
- spin_unlock(&mq->lock);
+ spin_unlock_bh(&mq->lock);
return ret;
}
EXPORT_SYMBOL(omap_mbox_msg_send);
len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
WARN_ON(len != sizeof(msg));
- if (mq->callback)
- mq->callback((void *)msg);
+ blocking_notifier_call_chain(&mq->mbox->notifier, len,
+ (void *)msg);
+ spin_lock_irq(&mq->lock);
+ if (mq->full) {
+ mq->full = false;
+ omap_mbox_enable_irq(mq->mbox, IRQ_RX);
+ }
+ spin_unlock_irq(&mq->lock);
}
}
while (!mbox_fifo_empty(mbox)) {
if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
omap_mbox_disable_irq(mbox, IRQ_RX);
- rq_full = true;
+ mq->full = true;
goto nomem;
}
int ret = 0;
struct omap_mbox_queue *mq;
- if (mbox->ops->startup) {
- mutex_lock(&mbox_configured_lock);
- if (!mbox_configured)
+ mutex_lock(&mbox_configured_lock);
+ if (!mbox_configured++) {
+ if (likely(mbox->ops->startup)) {
ret = mbox->ops->startup(mbox);
-
- if (ret) {
- mutex_unlock(&mbox_configured_lock);
- return ret;
- }
- mbox_configured++;
- mutex_unlock(&mbox_configured_lock);
- }
-
- ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
- mbox->name, mbox);
- if (ret) {
- printk(KERN_ERR
- "failed to register mailbox interrupt:%d\n", ret);
- goto fail_request_irq;
+ if (unlikely(ret))
+ goto fail_startup;
+ } else
+ goto fail_startup;
}
- mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
- if (!mq) {
- ret = -ENOMEM;
- goto fail_alloc_txq;
- }
- mbox->txq = mq;
+ if (!mbox->use_count++) {
+ ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
+ mbox->name, mbox);
+ if (unlikely(ret)) {
+ pr_err("failed to register mailbox interrupt:%d\n",
+ ret);
+ goto fail_request_irq;
+ }
+ mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
+ if (!mq) {
+ ret = -ENOMEM;
+ goto fail_alloc_txq;
+ }
+ mbox->txq = mq;
- mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
- if (!mq) {
- ret = -ENOMEM;
- goto fail_alloc_rxq;
+ mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
+ if (!mq) {
+ ret = -ENOMEM;
+ goto fail_alloc_rxq;
+ }
+ mbox->rxq = mq;
+ mq->mbox = mbox;
}
- mbox->rxq = mq;
-
+ mutex_unlock(&mbox_configured_lock);
return 0;
- fail_alloc_rxq:
+fail_alloc_rxq:
mbox_queue_free(mbox->txq);
- fail_alloc_txq:
+fail_alloc_txq:
free_irq(mbox->irq, mbox);
- fail_request_irq:
+fail_request_irq:
if (mbox->ops->shutdown)
mbox->ops->shutdown(mbox);
-
+ mbox->use_count--;
+fail_startup:
+ mbox_configured--;
+ mutex_unlock(&mbox_configured_lock);
return ret;
}
static void omap_mbox_fini(struct omap_mbox *mbox)
{
- free_irq(mbox->irq, mbox);
- tasklet_kill(&mbox->txq->tasklet);
- flush_work(&mbox->rxq->work);
- mbox_queue_free(mbox->txq);
- mbox_queue_free(mbox->rxq);
+ mutex_lock(&mbox_configured_lock);
+
+ if (!--mbox->use_count) {
+ free_irq(mbox->irq, mbox);
+ tasklet_kill(&mbox->txq->tasklet);
+ flush_work(&mbox->rxq->work);
+ mbox_queue_free(mbox->txq);
+ mbox_queue_free(mbox->rxq);
+ }
- if (mbox->ops->shutdown) {
- mutex_lock(&mbox_configured_lock);
- if (mbox_configured > 0)
- mbox_configured--;
- if (!mbox_configured)
+ if (likely(mbox->ops->shutdown)) {
+ if (!--mbox_configured)
mbox->ops->shutdown(mbox);
- mutex_unlock(&mbox_configured_lock);
}
+
+ mutex_unlock(&mbox_configured_lock);
}
-struct omap_mbox *omap_mbox_get(const char *name)
+struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
{
struct omap_mbox *mbox;
int ret;
if (ret)
return ERR_PTR(-ENODEV);
+ if (nb)
+ blocking_notifier_chain_register(&mbox->notifier, nb);
+
return mbox;
}
EXPORT_SYMBOL(omap_mbox_get);
-void omap_mbox_put(struct omap_mbox *mbox)
+void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb)
{
+ blocking_notifier_chain_unregister(&mbox->notifier, nb);
omap_mbox_fini(mbox);
}
EXPORT_SYMBOL(omap_mbox_put);
ret = PTR_ERR(mbox->dev);
goto err_out;
}
+
+ BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier);
}
return 0;
/* kfifo size sanity check: alignment and minimal size */
mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
- mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(mbox_msg_t));
+ mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
+ sizeof(mbox_msg_t));
return 0;
}
goto err_kfree;
}
- mcbsp->free = 0;
+ mcbsp->free = false;
mcbsp->reg_cache = reg_cache;
spin_unlock(&mcbsp->lock);
clk_disable(mcbsp->iclk);
spin_lock(&mcbsp->lock);
- mcbsp->free = 1;
+ mcbsp->free = true;
mcbsp->reg_cache = NULL;
err_kfree:
spin_unlock(&mcbsp->lock);
if (mcbsp->free)
dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
else
- mcbsp->free = 1;
+ mcbsp->free = true;
mcbsp->reg_cache = NULL;
spin_unlock(&mcbsp->lock);
spin_lock_init(&mcbsp->lock);
mcbsp->id = id + 1;
- mcbsp->free = 1;
+ mcbsp->free = true;
mcbsp->dma_tx_lch = -1;
mcbsp->dma_rx_lch = -1;
omap34xx_device_exit(mcbsp);
- clk_disable(mcbsp->fclk);
- clk_disable(mcbsp->iclk);
clk_put(mcbsp->fclk);
clk_put(mcbsp->iclk);
iounmap(mcbsp->io_base);
-
- mcbsp->fclk = NULL;
- mcbsp->iclk = NULL;
- mcbsp->free = 0;
- mcbsp->dev = NULL;
+ kfree(mcbsp);
}
return 0;
_omap_sram_reprogram_clock(dpllctl, ckctl);
}
-int __init omap1_sram_init(void)
+static int __init omap1_sram_init(void)
{
_omap_sram_reprogram_clock =
omap_sram_push(omap1_sram_reprogram_clock,
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/i2c-omap.h>
+#include <linux/pm_runtime.h>
/* I2C controller revisions */
#define OMAP_I2C_REV_2 0x20
void __iomem *base; /* virtual */
int irq;
int reg_shift; /* bit shift for I2C register addresses */
- struct clk *iclk; /* Interface clock */
- struct clk *fclk; /* Functional clock */
struct completion cmd_complete;
struct resource *ioarea;
u32 latency; /* maximum mpu wkup latency */
(i2c_dev->regs[reg] << i2c_dev->reg_shift));
}
-static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
+static void omap_i2c_unidle(struct omap_i2c_dev *dev)
{
- int ret;
+ struct platform_device *pdev;
+ struct omap_i2c_bus_platform_data *pdata;
- dev->iclk = clk_get(dev->dev, "ick");
- if (IS_ERR(dev->iclk)) {
- ret = PTR_ERR(dev->iclk);
- dev->iclk = NULL;
- return ret;
- }
+ WARN_ON(!dev->idle);
- dev->fclk = clk_get(dev->dev, "fck");
- if (IS_ERR(dev->fclk)) {
- ret = PTR_ERR(dev->fclk);
- if (dev->iclk != NULL) {
- clk_put(dev->iclk);
- dev->iclk = NULL;
- }
- dev->fclk = NULL;
- return ret;
- }
+ pdev = to_platform_device(dev->dev);
+ pdata = pdev->dev.platform_data;
- return 0;
-}
+ pm_runtime_get_sync(&pdev->dev);
-static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
-{
- clk_put(dev->fclk);
- dev->fclk = NULL;
- clk_put(dev->iclk);
- dev->iclk = NULL;
-}
-
-static void omap_i2c_unidle(struct omap_i2c_dev *dev)
-{
- WARN_ON(!dev->idle);
-
- clk_enable(dev->iclk);
- clk_enable(dev->fclk);
if (cpu_is_omap34xx()) {
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
static void omap_i2c_idle(struct omap_i2c_dev *dev)
{
+ struct platform_device *pdev;
+ struct omap_i2c_bus_platform_data *pdata;
u16 iv;
WARN_ON(dev->idle);
+ pdev = to_platform_device(dev->dev);
+ pdata = pdev->dev.platform_data;
+
dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
if (dev->rev >= OMAP_I2C_REV_ON_4430)
omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
}
dev->idle = 1;
- clk_disable(dev->fclk);
- clk_disable(dev->iclk);
+
+ pm_runtime_put_sync(&pdev->dev);
}
static int omap_i2c_init(struct omap_i2c_dev *dev)
unsigned long fclk_rate = 12000000;
unsigned long timeout;
unsigned long internal_clk = 0;
+ struct clk *fclk;
if (dev->rev >= OMAP_I2C_REV_2) {
/* Disable I2C controller before soft reset */
* always returns 12MHz for the functional clock, we can
* do this bit unconditionally.
*/
- fclk_rate = clk_get_rate(dev->fclk);
+ fclk = clk_get(dev->dev, "fck");
+ fclk_rate = clk_get_rate(fclk);
+ clk_put(fclk);
/* TRM for 5912 says the I2C clock must be prescaled to be
* between 7 - 12 MHz. The XOR input clock is typically
internal_clk = 9600;
else
internal_clk = 4000;
- fclk_rate = clk_get_rate(dev->fclk) / 1000;
+ fclk = clk_get(dev->dev, "fck");
+ fclk_rate = clk_get_rate(fclk) / 1000;
+ clk_put(fclk);
/* Compute prescaler divisor */
psc = fclk_rate / internal_clk;
else
dev->reg_shift = 2;
- if ((r = omap_i2c_get_clocks(dev)) != 0)
- goto err_iounmap;
-
if (cpu_is_omap44xx())
dev->regs = (u8 *) omap4_reg_map;
else
dev->regs = (u8 *) reg_map;
+ pm_runtime_enable(&pdev->dev);
omap_i2c_unidle(dev);
dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
err_unuse_clocks:
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
omap_i2c_idle(dev);
- omap_i2c_put_clocks(dev);
-err_iounmap:
iounmap(dev->base);
err_free_mem:
platform_set_drvdata(pdev, NULL);
free_irq(dev->irq, dev);
i2c_del_adapter(&dev->adapter);
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
- omap_i2c_put_clocks(dev);
iounmap(dev->base);
kfree(dev);
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
.probe = omap_i2c_probe,
.remove = omap_i2c_remove,
.driver = {
- .name = "i2c_omap",
+ .name = "omap_i2c",
.owner = THIS_MODULE,
},
};
MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:i2c_omap");
+MODULE_ALIAS("platform:omap_i2c");
tristate "Amstrad Delta (E3) mailboard support"
depends on MACH_AMS_DELTA
default y
- select AMS_DELTA_FIQ
---help---
Say Y here if you have an E3 and want to use its mailboard,
or any standard AT keyboard connected to the mailboard port.
{
if (p->capabilities & UART_CAP_SLEEP) {
if (p->capabilities & UART_CAP_EFR) {
- serial_outp(p, UART_LCR, 0xBF);
+ serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
serial_outp(p, UART_EFR, UART_EFR_ECB);
serial_outp(p, UART_LCR, 0);
}
serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
if (p->capabilities & UART_CAP_EFR) {
- serial_outp(p, UART_LCR, 0xBF);
+ serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
serial_outp(p, UART_EFR, 0);
serial_outp(p, UART_LCR, 0);
}
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
serial_outp(up, UART_MCR, UART_MCR_LOOP);
- serial_outp(up, UART_LCR, UART_LCR_DLAB);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
old_dl = serial_dl_read(up);
serial_dl_write(up, 0x0001);
serial_outp(up, UART_LCR, 0x03);
serial_inp(up, UART_RX);
serial_outp(up, UART_FCR, old_fcr);
serial_outp(up, UART_MCR, old_mcr);
- serial_outp(up, UART_LCR, UART_LCR_DLAB);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_dl_write(up, old_dl);
serial_outp(up, UART_LCR, old_lcr);
unsigned int id;
old_lcr = serial_inp(p, UART_LCR);
- serial_outp(p, UART_LCR, UART_LCR_DLAB);
+ serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
old_dll = serial_inp(p, UART_DLL);
old_dlm = serial_inp(p, UART_DLM);
* recommended for new designs).
*/
up->acr = 0;
- serial_out(up, UART_LCR, 0xBF);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, UART_EFR_ECB);
serial_out(up, UART_LCR, 0x00);
id1 = serial_icr_read(up, UART_ID1);
* Check for presence of the EFR when DLAB is set.
* Only ST16C650V1 UARTs pass this test.
*/
- serial_outp(up, UART_LCR, UART_LCR_DLAB);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
if (serial_in(up, UART_EFR) == 0) {
serial_outp(up, UART_EFR, 0xA8);
if (serial_in(up, UART_EFR) != 0) {
* Maybe it requires 0xbf to be written to the LCR.
* (other ST16C650V2 UARTs, TI16C752A, etc)
*/
- serial_outp(up, UART_LCR, 0xBF);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
DEBUG_AUTOCONF("EFRv2 ");
autoconfig_has_efr(up);
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
status1 = serial_in(up, UART_IIR) >> 5;
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
- serial_outp(up, UART_LCR, UART_LCR_DLAB);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
status2 = serial_in(up, UART_IIR) >> 5;
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
* We also initialise the EFR (if any) to zero for later. The
* EFR occupies the same register location as the FCR and IIR.
*/
- serial_outp(up, UART_LCR, 0xBF);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_outp(up, UART_EFR, 0);
serial_outp(up, UART_LCR, 0);
if (up->port.type == PORT_16C950) {
/* Wake up and initialize UART */
up->acr = 0;
- serial_outp(up, UART_LCR, 0xBF);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_outp(up, UART_EFR, UART_EFR_ECB);
serial_outp(up, UART_IER, 0);
serial_outp(up, UART_LCR, 0);
if (up->port.type == PORT_16850) {
unsigned char fctr;
- serial_outp(up, UART_LCR, 0xbf);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
if (termios->c_cflag & CRTSCTS)
efr |= UART_EFR_CTS;
- serial_outp(up, UART_LCR, 0xBF);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_outp(up, UART_EFR, efr);
}
unsigned char efr = 0;
up->lcr = serial_in(up, UART_LCR);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
up->efr = serial_in(up, UART_EFR);
serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
efr |= OMAP_UART_SW_RX;
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
up->mcr = serial_in(up, UART_MCR);
up->mcr |= UART_MCR_XONANY;
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
/* Enable special char function UARTi.EFR_REG[5] and
* load the new software flow control mode IXON or IXOFF
* and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
*/
serial_out(up, UART_EFR, efr | UART_EFR_SCD);
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
serial_out(up, UART_LCR, up->lcr);
* baud clock is not running
* DLL_REG and DLH_REG set to 0.
*/
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_DLL, 0);
serial_out(up, UART_DLM, 0);
serial_out(up, UART_LCR, 0);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
up->efr = serial_in(up, UART_EFR);
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
up->mcr = serial_in(up, UART_MCR);
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
/* FIFO ENABLE, DMA MODE */
serial_out(up, UART_FCR, up->fcr);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
if (up->use_dma) {
serial_out(up, UART_TI752_TLR, 0);
}
serial_out(up, UART_EFR, up->efr);
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_MCR, up->mcr);
/* Protocol, Baud Rate, and Interrupt Settings */
- serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_DISABLE);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
up->efr = serial_in(up, UART_EFR);
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
serial_out(up, UART_LCR, 0);
serial_out(up, UART_IER, 0);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
serial_out(up, UART_LCR, 0);
serial_out(up, UART_IER, up->ier);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, up->efr);
serial_out(up, UART_LCR, cval);
if (baud > 230400 && baud != 3000000)
- serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE13X);
+ serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_13X_MODE);
else
- serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE16X);
+ serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
/* Hardware Flow Control Configuration */
if (termios->c_cflag & CRTSCTS) {
efr |= (UART_EFR_CTS | UART_EFR_RTS);
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
up->mcr = serial_in(up, UART_MCR);
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
up->efr = serial_in(up, UART_EFR);
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
serial_out(up, UART_LCR, cval);
}
unsigned char efr;
dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
efr = serial_in(up, UART_EFR);
serial_out(up, UART_EFR, efr | UART_EFR_ECB);
serial_out(up, UART_LCR, 0);
serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, efr);
serial_out(up, UART_LCR, 0);
/* Enable module level wake up */
#ifndef __I2C_OMAP_H__
#define __I2C_OMAP_H__
+#include <linux/platform_device.h>
+
struct omap_i2c_bus_platform_data {
u32 clkrate;
void (*set_mpu_wkup_lat)(struct device *dev, long set);
+ int (*device_enable) (struct platform_device *pdev);
+ int (*device_shutdown) (struct platform_device *pdev);
+ int (*device_idle) (struct platform_device *pdev);
};
#endif
#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
+/*
+ * Access to some registers depends on register access / configuration
+ * mode.
+ */
+#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */
+#define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */
+
#define UART_MCR 4 /* Out: Modem Control Register */
#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
#define UART_OMAP_SYSS 0x16 /* System status register */
#define UART_OMAP_WER 0x17 /* Wake-up enable register */
+/*
+ * These are the definitions for the MDR1 register
+ */
+#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
+#define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */
+#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
+#define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */
+#define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */
+#define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */
+#define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */
+#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
+
#endif /* _LINUX_SERIAL_REG_H */
git.openpandora.org / pandora-kernel.git / commitdiff