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ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles
authorJisheng Zhang <jszhang@marvell.com>
Thu, 12 Jun 2014 09:38:40 +0000 (17:38 +0800)
committerSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Mon, 16 Jun 2014 11:09:04 +0000 (13:09 +0200)
For all BG2Q SoCs, 2 cycles is the best/correct value.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

No differences found
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