mips: ath79: ar933x: Fix ethernet PHY mismatch
authorWills Wang <wills.wang@live.com>
Sun, 22 May 2016 03:59:50 +0000 (11:59 +0800)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Wed, 25 May 2016 23:34:14 +0000 (01:34 +0200)
We need reset the Ethernet Switch analog part before operation,
or the build-in Ethernet PHY don't work.

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
arch/mips/mach-ath79/include/mach/ar71xx_regs.h
arch/mips/mach-ath79/reset.c

index a8e51cb..dabcad0 100644 (file)
 
 #define AR933X_RESET_GE1_MDIO                          BIT(23)
 #define AR933X_RESET_GE0_MDIO                          BIT(22)
+#define AR933X_RESET_ETH_SWITCH_ANALOG                 BIT(14)
 #define AR933X_RESET_GE1_MAC                           BIT(13)
 #define AR933X_RESET_WMAC                              BIT(11)
 #define AR933X_RESET_GE0_MAC                           BIT(9)
index 188eccb..a88bcbc 100644 (file)
@@ -81,7 +81,8 @@ static int eth_init_ar933x(void)
                                          MAP_NOCACHE);
        const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
                         AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
-                        AR933X_RESET_ETH_SWITCH;
+                        AR933X_RESET_ETH_SWITCH |
+                        AR933X_RESET_ETH_SWITCH_ANALOG;
 
        /* Clear MDIO slave EN bit. */
        clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));