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OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize
authorPaul Walmsley <paul@pwsan.com>
Mon, 15 Jun 2009 08:00:42 +0000 (02:00 -0600)
committerTony Lindgren <tony@atomide.com>
Mon, 15 Jun 2009 09:47:53 +0000 (12:47 +0300)
The original CDP kernel that this code comes from waited for 0x800
loops after switching the CORE DPLL M2 divider.  This does not appear
to be necessary.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

No differences found
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