drm/tegra: dpaux: Fix transfers larger than 4 bytes
authorThierry Reding <treding@nvidia.com>
Thu, 11 Jun 2015 16:33:48 +0000 (18:33 +0200)
committerThierry Reding <treding@nvidia.com>
Fri, 12 Jun 2015 14:22:46 +0000 (16:22 +0200)
The DPAUX read/write FIFO registers aren't sequential in the register
space, causing transfers larger than 4 bytes to cause accesses to non-
existing FIFO registers.

Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support")
Signed-off-by: Thierry Reding <treding@nvidia.com>

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