[NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 },
[NISTC_AO_START_SEL_REG] = { 0x184, 2 },
[NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 },
- [G_Autoincrement_Register(0)] = { 0x188, 2 },
- [G_Autoincrement_Register(1)] = { 0x18a, 2 },
+ [NISTC_G0_AUTOINC_REG] = { 0x188, 2 },
+ [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 },
[AO_Mode_3_Register] = { 0x18c, 2 },
[Joint_Reset_Register] = { 0x190, 2 },
[Interrupt_A_Enable_Register] = { 0x192, 2 },
}
static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
- [NITIO_G0_AUTO_INC] = { G_Autoincrement_Register(0), 2 },
- [NITIO_G1_AUTO_INC] = { G_Autoincrement_Register(1), 2 },
+ [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 },
+ [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
[NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
[NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
[NITIO_G0_HW_SAVE] = { G_HW_Save_Register(0), 4 },
#define NISTC_AO_TRIG_START1_SEL(x) (((x) & 0x1f) << 0)
#define NISTC_AO_TRIG_START1_SEL_MASK NISTC_AO_TRIG_START1_SEL(0x1f)
+#define NISTC_G0_AUTOINC_REG 68
+#define NISTC_G1_AUTOINC_REG 69
+
#define AI_Status_1_Register 2
#define Interrupt_A_St 0x8000
#define AI_FIFO_Full_St 0x4000
#define AI_External_Gate_Polarity _bit5
#define AI_External_Gate_Select(a) ((a) & 0x1f)
-#define G_Autoincrement_Register(a) (68+(a))
#define G_HW_Save_Register(a) (8+(a)*2)
#define G_HW_Save_Register_High(a) (8+(a)*2)
#define G_HW_Save_Register_Low(a) (9+(a)*2)