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OMAP3: PM: Fix for MPU power domain MEM BANK position
authorThara Gopinath <thara@ti.com>
Tue, 8 Dec 2009 23:33:15 +0000 (16:33 -0700)
committerpaul <paul@twilight.(none)>
Sat, 12 Dec 2009 00:00:42 +0000 (17:00 -0700)
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position

Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

No differences found
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