drm/nouveau/pwr: have rd/wr32 routines clobber data instead of addr

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
index 0a7b05f..8f29bad 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
@@ -51,12 +51,12 @@ time_next: .b32 0
 // $r0  - zero
 rd32:
        nv_iowr(NV_PPWR_MMIO_ADDR, $r14)
-       mov $r14 NV_PPWR_MMIO_CTRL_OP_RD
-       sethi $r14 NV_PPWR_MMIO_CTRL_TRIGGER
-       nv_iowr(NV_PPWR_MMIO_CTRL, $r14)
+       mov $r13 NV_PPWR_MMIO_CTRL_OP_RD
+       sethi $r13 NV_PPWR_MMIO_CTRL_TRIGGER
+       nv_iowr(NV_PPWR_MMIO_CTRL, $r13)
        rd32_wait:
-               nv_iord($r14, NV_PPWR_MMIO_CTRL)
-               and $r14 NV_PPWR_MMIO_CTRL_STATUS
+               nv_iord($r13, NV_PPWR_MMIO_CTRL)
+               and $r13 NV_PPWR_MMIO_CTRL_STATUS
                bra nz #rd32_wait
        nv_iord($r13, NV_PPWR_MMIO_DATA)
        ret
@@ -70,23 +70,25 @@ rd32:
 wr32:
        nv_iowr(NV_PPWR_MMIO_ADDR, $r14)
        nv_iowr(NV_PPWR_MMIO_DATA, $r13)
-       mov $r14 NV_PPWR_MMIO_CTRL_OP_WR
-       or $r14 NV_PPWR_MMIO_CTRL_MASK_B32_0
-       sethi $r14 NV_PPWR_MMIO_CTRL_TRIGGER
+       mov $r13 NV_PPWR_MMIO_CTRL_OP_WR
+       or $r13 NV_PPWR_MMIO_CTRL_MASK_B32_0
+       sethi $r13 NV_PPWR_MMIO_CTRL_TRIGGER
 
 #ifdef NVKM_FALCON_MMIO_TRAP
-       mov $r8 NV_PPWR_INTR_TRIGGER_USER1
-       nv_iowr(NV_PPWR_INTR_TRIGGER, $r8)
+       push $r13
+       mov $r13 NV_PPWR_INTR_TRIGGER_USER1
+       nv_iowr(NV_PPWR_INTR_TRIGGER, $r13)
        wr32_host:
-               nv_iord($r8, NV_PPWR_INTR)
-               and $r8 NV_PPWR_INTR_USER1
+               nv_iord($r13, NV_PPWR_INTR)
+               and $r13 NV_PPWR_INTR_USER1
                bra nz #wr32_host
+       pop $r13
 #endif
 
-       nv_iowr(NV_PPWR_MMIO_CTRL, $r14)
+       nv_iowr(NV_PPWR_MMIO_CTRL, $r13)
        wr32_wait:
-               nv_iord($r14, NV_PPWR_MMIO_CTRL)
-               and $r14 NV_PPWR_MMIO_CTRL_STATUS
+               nv_iord($r13, NV_PPWR_MMIO_CTRL)
+               and $r13 NV_PPWR_MMIO_CTRL_STATUS
                bra nz #wr32_wait
        ret
 

diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
index 9342e2d..255234a 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
@@ -786,13 +786,13 @@ uint32_t nv108_pwr_code[] = {
 /* 0x0004: rd32 */
        0xf607a040,
        0x04bd000e,
-       0xe3f0010e,
+       0xd3f0010d,
        0x07ac4001,
-       0xbd000ef6,
+       0xbd000df6,
 /* 0x0019: rd32_wait */
-       0x07ac4e04,
-       0xf100eecf,
-       0xf47000e4,
+       0x07ac4d04,
+       0xf100ddcf,
+       0xf47000d4,
        0xa44df61b,
        0x00ddcf07,
 /* 0x002e: wr32 */
@@ -800,14 +800,14 @@ uint32_t nv108_pwr_code[] = {
        0x000ef607,
        0xa44004bd,
        0x000df607,
-       0x020e04bd,
-       0xf0f0e5f0,
-       0xac4001e3,
-       0x000ef607,
+       0x020d04bd,
+       0xf0f0d5f0,
+       0xac4001d3,
+       0x000df607,
 /* 0x004e: wr32_wait */
-       0xac4e04bd,
-       0x00eecf07,
-       0x7000e4f1,
+       0xac4d04bd,
+       0x00ddcf07,
+       0x7000d4f1,
        0xf8f61bf4,
 /* 0x005d: nsec */
        0xcf2c0800,

diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
index 0fa4d7d..66a3109 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
@@ -787,15 +787,15 @@ uint32_t nva3_pwr_code[] = {
        0x07a007f1,
        0xd00604b6,
        0x04bd000e,
-       0xf001e7f0,
-       0x07f101e3,
+       0xf001d7f0,
+       0x07f101d3,
        0x04b607ac,
-       0x000ed006,
+       0x000dd006,
 /* 0x0022: rd32_wait */
-       0xe7f104bd,
-       0xe4b607ac,
-       0x00eecf06,
-       0x7000e4f1,
+       0xd7f104bd,
+       0xd4b607ac,
+       0x00ddcf06,
+       0x7000d4f1,
        0xf1f21bf4,
        0xb607a4d7,
        0xddcf06d4,
@@ -807,15 +807,15 @@ uint32_t nva3_pwr_code[] = {
        0xb607a407,
        0x0dd00604,
        0xf004bd00,
-       0xe5f002e7,
-       0x01e3f0f0,
+       0xd5f002d7,
+       0x01d3f0f0,
        0x07ac07f1,
        0xd00604b6,
-       0x04bd000e,
+       0x04bd000d,
 /* 0x006c: wr32_wait */
-       0x07ace7f1,
-       0xcf06e4b6,
-       0xe4f100ee,
+       0x07acd7f1,
+       0xcf06d4b6,
+       0xd4f100dd,
        0x1bf47000,
 /* 0x007f: nsec */
        0xf000f8f2,

diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
index 82c8e8b..1f49618 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
@@ -787,15 +787,15 @@ uint32_t nvc0_pwr_code[] = {
        0x07a007f1,
        0xd00604b6,
        0x04bd000e,
-       0xf001e7f0,
-       0x07f101e3,
+       0xf001d7f0,
+       0x07f101d3,
        0x04b607ac,
-       0x000ed006,
+       0x000dd006,
 /* 0x0022: rd32_wait */
-       0xe7f104bd,
-       0xe4b607ac,
-       0x00eecf06,
-       0x7000e4f1,
+       0xd7f104bd,
+       0xd4b607ac,
+       0x00ddcf06,
+       0x7000d4f1,
        0xf1f21bf4,
        0xb607a4d7,
        0xddcf06d4,
@@ -807,15 +807,15 @@ uint32_t nvc0_pwr_code[] = {
        0xb607a407,
        0x0dd00604,
        0xf004bd00,
-       0xe5f002e7,
-       0x01e3f0f0,
+       0xd5f002d7,
+       0x01d3f0f0,
        0x07ac07f1,
        0xd00604b6,
-       0x04bd000e,
+       0x04bd000d,
 /* 0x006c: wr32_wait */
-       0x07ace7f1,
-       0xcf06e4b6,
-       0xe4f100ee,
+       0x07acd7f1,
+       0xcf06d4b6,
+       0xd4f100dd,
        0x1bf47000,
 /* 0x007f: nsec */
        0xf000f8f2,

diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
index ce65e2a..c2be8db 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
@@ -786,14 +786,14 @@ uint32_t nvd0_pwr_code[] = {
 /* 0x0004: rd32 */
        0x07a007f1,
        0xbd000ed0,
-       0x01e7f004,
-       0xf101e3f0,
+       0x01d7f004,
+       0xf101d3f0,
        0xd007ac07,
-       0x04bd000e,
+       0x04bd000d,
 /* 0x001c: rd32_wait */
-       0x07ace7f1,
-       0xf100eecf,
-       0xf47000e4,
+       0x07acd7f1,
+       0xf100ddcf,
+       0xf47000d4,
        0xd7f1f51b,
        0xddcf07a4,
 /* 0x0033: wr32 */
@@ -802,14 +802,14 @@ uint32_t nvd0_pwr_code[] = {
        0x04bd000e,
        0x07a407f1,
        0xbd000dd0,
-       0x02e7f004,
-       0xf0f0e5f0,
-       0x07f101e3,
-       0x0ed007ac,
+       0x02d7f004,
+       0xf0f0d5f0,
+       0x07f101d3,
+       0x0dd007ac,
 /* 0x0057: wr32_wait */
        0xf104bd00,
-       0xcf07ace7,
-       0xe4f100ee,
+       0xcf07acd7,
+       0xd4f100dd,
        0x1bf47000,
 /* 0x0067: nsec */
        0xf000f8f5,