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drm/tegra: sor: Registers are 32-bit
authorThierry Reding <treding@nvidia.com>
Mon, 26 Jan 2015 15:02:48 +0000 (16:02 +0100)
committerThierry Reding <treding@nvidia.com>
Thu, 2 Apr 2015 16:46:16 +0000 (18:46 +0200)
Use a sized unsigned 32-bit data type (u32) to store register contents.
The SOR registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding <treding@nvidia.com>

No differences found
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