rockchip: clk: clk_rk3528: Add dummy CLK_REF_PCIE_INNER_PHY support

Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
the phy-rockchip-naneng-combphy driver on RK3528.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
index 06f2089..d58557f 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3528.c
+++ b/drivers/clk/rockchip/clk_rk3528.c
@@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
        /* Might occur in cru assigned-clocks, can be ignored here */
        case ACLK_BUS_VOPGL_ROOT:
        case BCLK_EMMC:
+       case CLK_REF_PCIE_INNER_PHY:
        case XIN_OSC0_DIV:
                ret = 0;
                break;