select BUILDTIME_EXTABLE_SORT if MMU
select CPU_PM if (SUSPEND || CPU_IDLE)
select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
- select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
+ select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
select GENERIC_CLOCKEVENTS_BROADCAST if SMP
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
select GENERIC_PCI_IOMAP
+ select GENERIC_SCHED_CLOCK
select GENERIC_SMP_IDLE_THREAD
select GENERIC_IDLE_POLL_SETUP
select GENERIC_STRNCPY_FROM_USER
and that the relevant menu configurations are displayed for
it.
+config ARCH_HAS_BANDGAP
+ bool
+
config GENERIC_HWEIGHT
bool
default y
select ARCH_REQUIRE_GPIOLIB
select AUTO_ZRELADDR
select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
select COMMON_CLK
select CPU_ARM720T
select GENERIC_CLOCKEVENTS
+ select MFD_SYSCON
select MULTI_IRQ_HANDLER
- select NEED_MACH_MEMORY_H
select SPARSE_IRQ
help
Support for Cirrus Logic 711x/721x/731x based boards.
config ARCH_KIRKWOOD
bool "Marvell Kirkwood"
+ select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select CPU_FEROCEON
select GENERIC_CLOCKEVENTS
bool "Qualcomm MSM"
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
+ select COMMON_CLK
select GENERIC_CLOCKEVENTS
- select HAVE_CLK
help
Support for Qualcomm MSM/QSD based systems. This runs on the
apps processor of the MSM/QSD and depends on a shared memory
config ARCH_SHMOBILE
bool "Renesas SH-Mobile / R-Mobile"
+ select ARM_PATCH_PHYS_VIRT
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU if SMP
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select MULTI_IRQ_HANDLER
- select NEED_MACH_MEMORY_H
select NO_IOPORT
- select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
+ select PINCTRL
select PM_GENERIC_DOMAINS if PM
select SPARSE_IRQ
help
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
+ select GPIO_SAMSUNG
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select MULTI_IRQ_HANDLER
select NEED_MACH_GPIO_H
select NEED_MACH_IO_H
+ select SAMSUNG_ATAGS
help
Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
select CLKSRC_MMIO
select CPU_V6
select GENERIC_CLOCKEVENTS
+ select GPIO_SAMSUNG
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select PLAT_SAMSUNG
select S3C_DEV_NAND
select S3C_GPIO_TRACK
+ select SAMSUNG_ATAGS
select SAMSUNG_CLKSRC
select SAMSUNG_GPIOLIB_4BIT
select SAMSUNG_IRQ_VIC_TIMER
+ select SAMSUNG_WDT_RESET
select USB_ARCH_HAS_OHCI
help
Samsung S3C64XX series based systems
select CLKSRC_MMIO
select CPU_V6
select GENERIC_CLOCKEVENTS
+ select GPIO_SAMSUNG
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_GPIO_H
+ select SAMSUNG_WDT_RESET
+ select SAMSUNG_ATAGS
help
Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
SMDK6450.
select CLKSRC_MMIO
select CPU_V7
select GENERIC_CLOCKEVENTS
+ select GPIO_SAMSUNG
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_GPIO_H
+ select SAMSUNG_WDT_RESET
+ select SAMSUNG_ATAGS
help
Samsung S5PC100 series based systems
select CLKSRC_MMIO
select CPU_V7
select GENERIC_CLOCKEVENTS
+ select GPIO_SAMSUNG
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_GPIO_H
select NEED_MACH_MEMORY_H
+ select SAMSUNG_ATAGS
help
Samsung S5PV210/S5PC110 series based systems
bool "Samsung EXYNOS"
select ARCH_HAS_CPUFREQ
select ARCH_HAS_HOLES_MEMORYMODEL
+ select ARCH_REQUIRE_GPIOLIB
select ARCH_SPARSEMEM_ENABLE
+ select ARM_GIC
select CLKDEV_LOOKUP
select COMMON_CLK
select CPU_V7
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
- select NEED_MACH_GPIO_H
select NEED_MACH_MEMORY_H
+ select SPARSE_IRQ
+ select USE_OF
help
Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
Support for the StrongARM based Digital DNARD machine, also known
as "Shark" (<http://www.shark-linux.de/shark.html>).
-config ARCH_U300
- bool "ST-Ericsson U300 Series"
- depends on MMU
- select ARCH_REQUIRE_GPIOLIB
- select ARM_AMBA
- select ARM_PATCH_PHYS_VIRT
- select ARM_VIC
- select CLKDEV_LOOKUP
- select CLKSRC_MMIO
- select COMMON_CLK
- select CPU_ARM926T
- select GENERIC_CLOCKEVENTS
- select HAVE_TCM
- select SPARSE_IRQ
- help
- Support for ST-Ericsson U300 series mobile platforms.
-
config ARCH_DAVINCI
bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL
select GENERIC_IRQ_CHIP
select HAVE_IDE
select NEED_MACH_GPIO_H
+ select TI_PRIV_EDMA
select USE_OF
select ZONE_DMA
help
comment "CPU Core family selection"
-config ARCH_MULTI_V4
- bool "ARMv4 based platforms (FA526, StrongARM)"
- depends on !ARCH_MULTI_V6_V7
- select ARCH_MULTI_V4_V5
-
config ARCH_MULTI_V4T
bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
depends on !ARCH_MULTI_V6_V7
select ARCH_MULTI_V4_V5
+ select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
+ CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
+ CPU_ARM925T || CPU_ARM940T)
config ARCH_MULTI_V5
bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
depends on !ARCH_MULTI_V6_V7
select ARCH_MULTI_V4_V5
+ select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
+ CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
+ CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
config ARCH_MULTI_V4_V5
bool
source "arch/arm/mach-ixp4xx/Kconfig"
+source "arch/arm/mach-keystone/Kconfig"
+
source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
+source "arch/arm/mach-nspire/Kconfig"
+
source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-omap1/Kconfig"
source "arch/arm/mach-realview/Kconfig"
+source "arch/arm/mach-rockchip/Kconfig"
+
source "arch/arm/mach-sa1100/Kconfig"
source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/mach-spear/Kconfig"
+source "arch/arm/mach-sti/Kconfig"
+
source "arch/arm/mach-s3c24xx/Kconfig"
if ARCH_S3C64XX
select DMABOUNCE
source "drivers/pci/Kconfig"
+source "drivers/pci/pcie/Kconfig"
source "drivers/pcmcia/Kconfig"
depends on CPU_V6K || CPU_V7
depends on GENERIC_CLOCKEVENTS
depends on HAVE_SMP
- depends on MMU
+ depends on MMU || ARM_MPU
select USE_GENERIC_SMP_HELPERS
help
This enables support for systems with more than one CPU. If you have
config SMP_ON_UP
bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
- depends on SMP && !XIP_KERNEL
+ depends on SMP && !XIP_KERNEL && MMU
default y
help
SMP kernels contain instructions which fail on non-SMP processors.
config HOTPLUG_CPU
bool "Support for hot-pluggable CPUs"
- depends on SMP && HOTPLUG
+ depends on SMP
help
Say Y here to experiment with turning CPUs off and on. CPUs
can be controlled through /sys/devices/system/cpu.
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 512 if SOC_OMAP5
+ default 512 if ARCH_KEYSTONE
default 392 if ARCH_U8500
default 352 if ARCH_VT8500
default 288 if ARCH_SUNXI
config THUMB2_KERNEL
bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
- depends on CPU_V7 && !CPU_V6 && !CPU_V6K
+ depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
default y if CPU_THUMBONLY
select AEABI
select ARM_ASM_UNIFIED
Enable hardware performance counter support for perf events. If
disabled, perf events will use software events only.
+config SYS_SUPPORTS_HUGETLBFS
+ def_bool y
+ depends on ARM_LPAE
+
+config HAVE_ARCH_TRANSPARENT_HUGEPAGE
+ def_bool y
+ depends on ARM_LPAE
+
source "mm/Kconfig"
config FORCE_MAX_ZONEORDER
config AUTO_ZRELADDR
bool "Auto calculation of the decompressed kernel image address"
- depends on !ZBOOT_ROM && !ARCH_U300
+ depends on !ZBOOT_ROM
help
ZRELADDR is the physical address where the decompressed kernel
image will be placed. If AUTO_ZRELADDR is selected, the address
if ARCH_HAS_CPUFREQ
source "drivers/cpufreq/Kconfig"
-
-config CPU_FREQ_S3C
- bool
- help
- Internal configuration node for common cpufreq on Samsung SoC
-
-config CPU_FREQ_S3C24XX
- bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
- depends on ARCH_S3C24XX && CPU_FREQ
- select CPU_FREQ_S3C
- help
- This enables the CPUfreq driver for the Samsung S3C24XX family
- of CPUs.
-
- For details, take a look at <file:Documentation/cpu-freq>.
-
- If in doubt, say N.
-
-config CPU_FREQ_S3C24XX_PLL
- bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
- depends on CPU_FREQ_S3C24XX
- help
- Compile in support for changing the PLL frequency from the
- S3C24XX series CPUfreq driver. The PLL takes time to settle
- after a frequency change, so by default it is not enabled.
-
- This also means that the PLL tables for the selected CPU(s) will
- be built which may increase the size of the kernel image.
-
-config CPU_FREQ_S3C24XX_DEBUG
- bool "Debug CPUfreq Samsung driver core"
- depends on CPU_FREQ_S3C24XX
- help
- Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
-
-config CPU_FREQ_S3C24XX_IODEBUG
- bool "Debug CPUfreq Samsung driver IO timing"
- depends on CPU_FREQ_S3C24XX
- help
- Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
-
-config CPU_FREQ_S3C24XX_DEBUGFS
- bool "Export debugfs for CPUFreq"
- depends on CPU_FREQ_S3C24XX && DEBUG_FS
- help
- Export status information via debugfs.
-
endif
source "drivers/cpuidle/Kconfig"
# Object file lists.
-obj-y := elf.o entry-armv.o entry-common.o irq.o opcodes.o \
+obj-y := elf.o entry-common.o irq.o opcodes.o \
- process.o ptrace.o return_address.o sched_clock.o \
+ process.o ptrace.o return_address.o \
setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
obj-$(CONFIG_ATAGS) += atags_parse.o
obj-$(CONFIG_ATAGS_PROC) += atags_proc.o
obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
+ifeq ($(CONFIG_CPU_V7M),y)
+obj-y += entry-v7m.o
+else
+obj-y += entry-armv.o
+endif
+
obj-$(CONFIG_OC_ETM) += etm.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ISA_DMA_API) += dma.o
obj-$(CONFIG_ISA_DMA) += dma-isa.o
obj-$(CONFIG_PCI) += bios32.o isa.o
obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o
-obj-$(CONFIG_SMP) += smp.o smp_tlb.o
+obj-$(CONFIG_SMP) += smp.o
+ifdef CONFIG_MMU
+obj-$(CONFIG_SMP) += smp_tlb.o
+endif
obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o
obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arch_timer.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o
-obj-$(CONFIG_ARM_PSCI) += psci.o
+ifeq ($(CONFIG_ARM_PSCI),y)
+obj-y += psci.o
+obj-$(CONFIG_SMP) += psci_smp.o
+endif
extra-y := $(head-y) vmlinux.lds
#include <linux/stat.h>
#include <linux/sys_soc.h>
#include <linux/termios.h>
-#include <video/vga.h>
+ #include <linux/sched_clock.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/setup.h>
#include <asm/param.h> /* HZ */
#include <asm/mach-types.h>
- #include <asm/sched_clock.h>
#include <mach/lm.h>
#include <mach/irqs.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
-#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include "common.h"
+#include "pci_v3.h"
/* Base address to the AP system controller */
void __iomem *ap_syscon_base;
/*
* Logical Physical
- * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
- * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
- * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
- * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
* ef000000 Cache flush
* f1000000 10000000 Core module registers
* f1100000 11000000 System controller registers
.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
.length = SZ_4K,
.type = MT_DEVICE
- }, {
- .virtual = (unsigned long)PCI_MEMORY_VADDR,
- .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
- .length = SZ_16M,
- .type = MT_DEVICE
- }, {
- .virtual = (unsigned long)PCI_CONFIG_VADDR,
- .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
- .length = SZ_16M,
- .type = MT_DEVICE
- }, {
- .virtual = (unsigned long)PCI_V3_VADDR,
- .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
- .length = SZ_64K,
- .type = MT_DEVICE
}
};
static void __init ap_map_io(void)
{
iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
- vga_base = (unsigned long)PCI_MEMORY_VADDR;
- pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
+ pci_v3_early_init();
}
#ifdef CONFIG_PM
* for eventual deletion.
*/
+static struct platform_device pci_v3_device = {
+ .name = "pci-v3",
+ .id = 0,
+};
+
static struct resource cfi_flash_resource = {
.start = INTEGRATOR_FLASH_BASE,
.end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
unsigned long sc_dec;
int i;
+ platform_device_register(&pci_v3_device);
platform_device_register(&cfi_flash_device);
ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
#include <linux/export.h>
#include <linux/gpio.h>
#include <linux/cpu.h>
+ #include <linux/sched_clock.h>
#include <mach/udc.h>
#include <mach/hardware.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/irq.h>
- #include <asm/sched_clock.h>
#include <asm/system_misc.h>
#include <asm/mach/map.h>
* fallback to the default.
*/
-static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
+static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
unsigned int mtype, void *caller)
{
if (!is_pci_memory(addr))
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
+ #include <linux/sched_clock.h>
#include <asm/mach/time.h>
#include <asm/smp_twd.h>
- #include <asm/sched_clock.h>
#include "omap_hwmod.h"
#include "omap_device.h"
2, "timer_sys_ck", NULL);
#endif /* CONFIG_ARCH_OMAP2 */
-#ifdef CONFIG_ARCH_OMAP3
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
2, "timer_sys_ck", NULL);
OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+ #include <linux/sched_clock.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-
/* Generic stuff */
- #include <asm/sched_clock.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
-#include "timer.h"
-
/*
* APP side special timer registers
* This timer contains four timers which can fire an interrupt each.
#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
+static void __iomem *u300_timer_base;
+
/*
* The u300_set_mode() function is always called first, if we
* have oneshot timer active, the oneshot scheduling function
case CLOCK_EVT_MODE_PERIODIC:
/* Disable interrupts on GPT1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+ u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Disable GP1 while we're reprogramming it. */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+ u300_timer_base + U300_TIMER_APP_DGPT1);
/*
* Set the periodic mode to a certain number of ticks per
* jiffy.
*/
writel(TICKS_PER_JIFFY,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+ u300_timer_base + U300_TIMER_APP_GPT1TC);
/*
* Set continuous mode, so the timer keeps triggering
* interrupts.
*/
writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+ u300_timer_base + U300_TIMER_APP_SGPT1M);
/* Enable timer interrupts */
writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+ u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Then enable the OS timer again */
writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+ u300_timer_base + U300_TIMER_APP_EGPT1);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* Just break; here? */
*/
/* Disable interrupts on GPT1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+ u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Disable GP1 while we're reprogramming it. */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+ u300_timer_base + U300_TIMER_APP_DGPT1);
/*
* Expire far in the future, u300_set_next_event() will be
* called soon...
*/
- writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+ writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
/* We run one shot per tick here! */
writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+ u300_timer_base + U300_TIMER_APP_SGPT1M);
/* Enable interrupts for this timer */
writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+ u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Enable timer */
writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+ u300_timer_base + U300_TIMER_APP_EGPT1);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
/* Disable interrupts on GP1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+ u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Disable GP1 */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+ u300_timer_base + U300_TIMER_APP_DGPT1);
break;
case CLOCK_EVT_MODE_RESUME:
/* Ignore this call */
{
/* Disable interrupts on GPT1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+ u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Disable GP1 while we're reprogramming it. */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+ u300_timer_base + U300_TIMER_APP_DGPT1);
/* Reset the General Purpose timer 1. */
writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+ u300_timer_base + U300_TIMER_APP_RGPT1);
/* IRQ in n * cycles */
- writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+ writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
/*
* We run one shot per tick here! (This is necessary to reconfigure,
* the timer will tilt if you don't!)
*/
writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+ u300_timer_base + U300_TIMER_APP_SGPT1M);
/* Enable timer interrupts */
writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+ u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Then enable the OS timer again */
writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+ u300_timer_base + U300_TIMER_APP_EGPT1);
return 0;
}
{
struct clock_event_device *evt = &clockevent_u300_1mhz;
/* ACK/Clear timer IRQ for the APP GPT1 Timer */
+
writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
+ u300_timer_base + U300_TIMER_APP_GPT1IA);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static u32 notrace u300_read_sched_clock(void)
{
- return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+ return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
+}
+
+static unsigned long u300_read_current_timer(void)
+{
+ return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
}
+static struct delay_timer u300_delay_timer;
/*
* This sets up the system timers, clock source and clock event.
*/
-void __init u300_timer_init(void)
+static void __init u300_timer_init_of(struct device_node *np)
{
+ struct resource irq_res;
+ int irq;
struct clk *clk;
unsigned long rate;
+ u300_timer_base = of_iomap(np, 0);
+ if (!u300_timer_base)
+ panic("could not ioremap system timer\n");
+
+ /* Get the IRQ for the GP1 timer */
+ irq = of_irq_to_resource(np, 2, &irq_res);
+ if (irq <= 0)
+ panic("no IRQ for system timer\n");
+
+ pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
+
/* Clock the interrupt controller */
- clk = clk_get_sys("apptimer", NULL);
+ clk = of_clk_get(np, 0);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
rate = clk_get_rate(clk);
setup_sched_clock(u300_read_sched_clock, 32, rate);
+ u300_delay_timer.read_current_timer = &u300_read_current_timer;
+ u300_delay_timer.freq = rate;
+ register_current_timer_delay(&u300_delay_timer);
+
/*
* Disable the "OS" and "DD" timers - these are designed for Symbian!
* Example usage in cnh1601578 cpu subsystem pd_timer_app.c
*/
writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
+ u300_timer_base + U300_TIMER_APP_CRC);
writel(U300_TIMER_APP_ROST_TIMER_RESET,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
+ u300_timer_base + U300_TIMER_APP_ROST);
writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
+ u300_timer_base + U300_TIMER_APP_DOST);
writel(U300_TIMER_APP_RDDT_TIMER_RESET,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
+ u300_timer_base + U300_TIMER_APP_RDDT);
writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
+ u300_timer_base + U300_TIMER_APP_DDDT);
/* Reset the General Purpose timer 1. */
writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+ u300_timer_base + U300_TIMER_APP_RGPT1);
/* Set up the IRQ handler */
- setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
+ setup_irq(irq, &u300_timer_irq);
/* Reset the General Purpose timer 2 */
writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
+ u300_timer_base + U300_TIMER_APP_RGPT2);
/* Set this timer to run around forever */
- writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
+ writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
/* Set continuous mode so it wraps around */
writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
+ u300_timer_base + U300_TIMER_APP_SGPT2M);
/* Disable timer interrupts */
writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
+ u300_timer_base + U300_TIMER_APP_GPT2IE);
/* Then enable the GP2 timer to use as a free running us counter */
writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
- U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
+ u300_timer_base + U300_TIMER_APP_EGPT2);
/* Use general purpose timer 2 as clock source */
- if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
+ if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
"GPT2", rate, 300, 32, clocksource_mmio_readl_up))
pr_err("timer: failed to initialize U300 clock source\n");
* used by hrtimers!
*/
}
+
+CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
+ u300_timer_init_of);
* It would be far better for everyone if the Guest had its own clock, but
* until then the Host gives us the time on every interrupt.
*/
- static unsigned long lguest_get_wallclock(void)
+ static void lguest_get_wallclock(struct timespec *now)
{
- return lguest_data.time.tv_sec;
+ *now = lguest_data.time;
}
/*
new_cpu_data.x86_capability[0] = cpuid_edx(1);
/* Math is always hard! */
- new_cpu_data.hard_math = 1;
+ set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU);
/* We don't have features. We have puppies! Puppies! */
#ifdef CONFIG_X86_MCE
return status;
}
- int efi_set_rtc_mmss(unsigned long nowtime)
+ int efi_set_rtc_mmss(const struct timespec *now)
{
+ unsigned long nowtime = now->tv_sec;
efi_status_t status;
efi_time_t eft;
efi_time_cap_t cap;
return 0;
}
- unsigned long efi_get_time(void)
+ void efi_get_time(struct timespec *now)
{
efi_status_t status;
efi_time_t eft;
if (status != EFI_SUCCESS)
pr_err("Oops: efitime: can't read time!\n");
- return mktime(eft.year, eft.month, eft.day, eft.hour,
- eft.minute, eft.second);
+ now->tv_sec = mktime(eft.year, eft.month, eft.day, eft.hour,
+ eft.minute, eft.second);
+ now->tv_nsec = 0;
}
/*
va = efi_ioremap(md->phys_addr, size,
md->type, md->attribute);
+ if (!(md->attribute & EFI_MEMORY_RUNTIME)) {
+ if (!va)
+ pr_err("ioremap of 0x%llX failed!\n",
+ (unsigned long long)md->phys_addr);
+ continue;
+ }
+
md->virt_addr = (u64) (unsigned long) va;
if (!va) {
#include <linux/kernel_stat.h>
#include <linux/math64.h>
#include <linux/gfp.h>
+#include <linux/slab.h>
+ #include <linux/pvclock_gtod.h>
#include <asm/pvclock.h>
#include <asm/xen/hypervisor.h>
/* snapshots of runstate info */
static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
-/* unused ns of stolen and blocked time */
+/* unused ns of stolen time */
static DEFINE_PER_CPU(u64, xen_residual_stolen);
-static DEFINE_PER_CPU(u64, xen_residual_blocked);
/* return an consistent snapshot of 64-bit time/counter value */
static u64 get64(const u64 *p)
{
struct vcpu_runstate_info state;
struct vcpu_runstate_info *snap;
- s64 blocked, runnable, offline, stolen;
+ s64 runnable, offline, stolen;
cputime_t ticks;
get_runstate_snapshot(&state);
snap = &__get_cpu_var(xen_runstate_snapshot);
/* work out how much time the VCPU has not been runn*ing* */
- blocked = state.time[RUNSTATE_blocked] - snap->time[RUNSTATE_blocked];
runnable = state.time[RUNSTATE_runnable] - snap->time[RUNSTATE_runnable];
offline = state.time[RUNSTATE_offline] - snap->time[RUNSTATE_offline];
ticks = iter_div_u64_rem(stolen, NS_PER_TICK, &stolen);
__this_cpu_write(xen_residual_stolen, stolen);
account_steal_ticks(ticks);
-
- /* Add the appropriate number of ticks of blocked time,
- including any left-overs from last time. */
- blocked += __this_cpu_read(xen_residual_blocked);
-
- if (blocked < 0)
- blocked = 0;
-
- ticks = iter_div_u64_rem(blocked, NS_PER_TICK, &blocked);
- __this_cpu_write(xen_residual_blocked, blocked);
- account_idle_ticks(ticks);
}
/* Get the TSC speed from Xen */
put_cpu_var(xen_vcpu);
}
- static unsigned long xen_get_wallclock(void)
+ static void xen_get_wallclock(struct timespec *now)
{
- struct timespec ts;
+ xen_read_wallclock(now);
+ }
- xen_read_wallclock(&ts);
- return ts.tv_sec;
+ static int xen_set_wallclock(const struct timespec *now)
+ {
+ return -1;
}
- static int xen_set_wallclock(unsigned long now)
+ static int xen_pvclock_gtod_notify(struct notifier_block *nb,
+ unsigned long was_set, void *priv)
{
+ /* Protected by the calling core code serialization */
+ static struct timespec next_sync;
+
struct xen_platform_op op;
- int rc;
+ struct timespec now;
- /* do nothing for domU */
- if (!xen_initial_domain())
- return -1;
+ now = __current_kernel_time();
+
+ /*
+ * We only take the expensive HV call when the clock was set
+ * or when the 11 minutes RTC synchronization time elapsed.
+ */
+ if (!was_set && timespec_compare(&now, &next_sync) < 0)
+ return NOTIFY_OK;
op.cmd = XENPF_settime;
- op.u.settime.secs = now;
- op.u.settime.nsecs = 0;
+ op.u.settime.secs = now.tv_sec;
+ op.u.settime.nsecs = now.tv_nsec;
op.u.settime.system_time = xen_clocksource_read();
- rc = HYPERVISOR_dom0_op(&op);
- WARN(rc != 0, "XENPF_settime failed: now=%ld\n", now);
+ (void)HYPERVISOR_dom0_op(&op);
- return rc;
+ /*
+ * Move the next drift compensation time 11 minutes
+ * ahead. That's emulating the sync_cmos_clock() update for
+ * the hardware RTC.
+ */
+ next_sync = now;
+ next_sync.tv_sec += 11 * 60;
+
+ return NOTIFY_OK;
}
+ static struct notifier_block xen_pvclock_gtod_notifier = {
+ .notifier_call = xen_pvclock_gtod_notify,
+ };
+
static struct clocksource xen_clocksource __read_mostly = {
.name = "xen",
.rating = 400,
static const struct clock_event_device *xen_clockevent =
&xen_timerop_clockevent;
-static DEFINE_PER_CPU(struct clock_event_device, xen_clock_events) = { .irq = -1 };
+
+struct xen_clock_event_device {
+ struct clock_event_device evt;
+ char *name;
+};
+static DEFINE_PER_CPU(struct xen_clock_event_device, xen_clock_events) = { .evt.irq = -1 };
static irqreturn_t xen_timer_interrupt(int irq, void *dev_id)
{
- struct clock_event_device *evt = &__get_cpu_var(xen_clock_events);
+ struct clock_event_device *evt = &__get_cpu_var(xen_clock_events).evt;
irqreturn_t ret;
ret = IRQ_NONE;
return ret;
}
+void xen_teardown_timer(int cpu)
+{
+ struct clock_event_device *evt;
+ BUG_ON(cpu == 0);
+ evt = &per_cpu(xen_clock_events, cpu).evt;
+
+ if (evt->irq >= 0) {
+ unbind_from_irqhandler(evt->irq, NULL);
+ evt->irq = -1;
+ kfree(per_cpu(xen_clock_events, cpu).name);
+ per_cpu(xen_clock_events, cpu).name = NULL;
+ }
+}
+
void xen_setup_timer(int cpu)
{
- const char *name;
+ char *name;
struct clock_event_device *evt;
int irq;
- evt = &per_cpu(xen_clock_events, cpu);
+ evt = &per_cpu(xen_clock_events, cpu).evt;
WARN(evt->irq >= 0, "IRQ%d for CPU%d is already allocated\n", evt->irq, cpu);
+ if (evt->irq >= 0)
+ xen_teardown_timer(cpu);
printk(KERN_INFO "installing Xen timer for CPU %d\n", cpu);
evt->cpumask = cpumask_of(cpu);
evt->irq = irq;
+ per_cpu(xen_clock_events, cpu).name = name;
}
-void xen_teardown_timer(int cpu)
-{
- struct clock_event_device *evt;
- BUG_ON(cpu == 0);
- evt = &per_cpu(xen_clock_events, cpu);
- unbind_from_irqhandler(evt->irq, NULL);
- evt->irq = -1;
-}
void xen_setup_cpu_clockevents(void)
{
BUG_ON(preemptible());
- clockevents_register_device(&__get_cpu_var(xen_clock_events));
+ clockevents_register_device(&__get_cpu_var(xen_clock_events).evt);
}
void xen_timer_resume(void)
xen_setup_runstate_info(cpu);
xen_setup_timer(cpu);
xen_setup_cpu_clockevents();
+
+ if (xen_initial_domain())
+ pvclock_gtod_register_notifier(&xen_pvclock_gtod_notifier);
}
void __init xen_init_time_ops(void)
x86_platform.calibrate_tsc = xen_tsc_khz;
x86_platform.get_wallclock = xen_get_wallclock;
- x86_platform.set_wallclock = xen_set_wallclock;
+ /* Dom0 uses the native method to set the hardware RTC. */
+ if (!xen_initial_domain())
+ x86_platform.set_wallclock = xen_set_wallclock;
}
#ifdef CONFIG_XEN_PVHVM
config DW_APB_TIMER_OF
bool
+ select DW_APB_TIMER
+ select CLKSRC_OF
config ARMADA_370_XP_TIMER
bool
Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
for all devicetree enabled platforms. This driver will be
needed only on systems that do not have the Exynos MCT available.
+
+ config VF_PIT_TIMER
+ bool
+ help
+ Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
* DBx500-PRCMU Timer
* The PRCMU has 5 timers which are available in a always-on
* power domain. We use the Timer 4 for our always-on clock
- * source on DB8500 and Timer 3 on DB5500.
+ * source on DB8500.
*/
#include <linux/clockchips.h>
#include <linux/clksrc-dbx500-prcmu.h>
-
- #include <asm/sched_clock.h>
+ #include <linux/sched_clock.h>
#define RATE_32K 32768
static void __iomem *clksrc_dbx500_timer_base;
-static cycle_t clksrc_dbx500_prcmu_read(struct clocksource *cs)
+static cycle_t notrace clksrc_dbx500_prcmu_read(struct clocksource *cs)
{
+ void __iomem *base = clksrc_dbx500_timer_base;
u32 count, count2;
do {
- count = readl(clksrc_dbx500_timer_base +
- PRCMU_TIMER_DOWNCOUNT);
- count2 = readl(clksrc_dbx500_timer_base +
- PRCMU_TIMER_DOWNCOUNT);
+ count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
+ count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
} while (count2 != count);
/* Negate because the timer is a decrementing counter */
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
-
- #include <asm/mach/time.h>
- #include <asm/sched_clock.h>
+#include <linux/clk.h>
+ #include <linux/sched_clock.h>
static void timer_get_base_and_rate(struct device_node *np,
void __iomem **base, u32 *rate)
{
+ struct clk *timer_clk;
+ struct clk *pclk;
+
*base = of_iomap(np, 0);
if (!*base)
panic("Unable to map regs for %s", np->name);
+ /*
+ * Not all implementations use a periphal clock, so don't panic
+ * if it's not present
+ */
+ pclk = of_clk_get_by_name(np, "pclk");
+ if (!IS_ERR(pclk))
+ if (clk_prepare_enable(pclk))
+ pr_warn("pclk for %s is present, but could not be activated\n",
+ np->name);
+
+ timer_clk = of_clk_get_by_name(np, "timer");
+ if (IS_ERR(timer_clk))
+ goto try_clock_freq;
+
+ if (!clk_prepare_enable(timer_clk)) {
+ *rate = clk_get_rate(timer_clk);
+ return;
+ }
+
+try_clock_freq:
if (of_property_read_u32(np, "clock-freq", rate) &&
of_property_read_u32(np, "clock-frequency", rate))
- panic("No clock-frequency property for %s", np->name);
+ panic("No clock nor clock-frequency property for %s", np->name);
}
static void add_clockevent(struct device_node *event_timer)
u32 irq, rate;
irq = irq_of_parse_and_map(event_timer, 0);
- if (irq == NO_IRQ)
+ if (irq == 0)
panic("No IRQ for clock event timer");
timer_get_base_and_rate(event_timer, &iobase, &rate);
dw_apb_clockevent_register(ced);
}
+static void __iomem *sched_io_base;
+static u32 sched_rate;
+
static void add_clocksource(struct device_node *source_timer)
{
void __iomem *iobase;
dw_apb_clocksource_start(cs);
dw_apb_clocksource_register(cs);
-}
-static void __iomem *sched_io_base;
+ /*
+ * Fallback to use the clocksource as sched_clock if no separate
+ * timer is found. sched_io_base then points to the current_value
+ * register of the clocksource timer.
+ */
+ sched_io_base = iobase + 0x04;
+ sched_rate = rate;
+}
static u32 read_sched_clock(void)
{
static void init_sched_clock(void)
{
struct device_node *sched_timer;
- u32 rate;
sched_timer = of_find_matching_node(NULL, sptimer_ids);
- if (!sched_timer)
- panic("No RTC for sched clock to use");
+ if (sched_timer) {
+ timer_get_base_and_rate(sched_timer, &sched_io_base,
+ &sched_rate);
+ of_node_put(sched_timer);
+ }
- timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
- of_node_put(sched_timer);
-
- setup_sched_clock(read_sched_clock, 32, rate);
+ setup_sched_clock(read_sched_clock, 32, sched_rate);
}
-static const struct of_device_id osctimer_ids[] __initconst = {
- { .compatible = "picochip,pc3x2-timer" },
- { .compatible = "snps,dw-apb-timer-osc" },
- {},
-};
-
-void __init dw_apb_timer_init(void)
+static int num_called;
+static void __init dw_apb_timer_init(struct device_node *timer)
{
- struct device_node *event_timer, *source_timer;
-
- event_timer = of_find_matching_node(NULL, osctimer_ids);
- if (!event_timer)
- panic("No timer for clockevent");
- add_clockevent(event_timer);
-
- source_timer = of_find_matching_node(event_timer, osctimer_ids);
- if (!source_timer)
- panic("No timer for clocksource");
- add_clocksource(source_timer);
-
- of_node_put(source_timer);
-
- init_sched_clock();
+ switch (num_called) {
+ case 0:
+ pr_debug("%s: found clockevent timer\n", __func__);
+ add_clockevent(timer);
+ of_node_put(timer);
+ break;
+ case 1:
+ pr_debug("%s: found clocksource timer\n", __func__);
+ add_clocksource(timer);
+ of_node_put(timer);
+ init_sched_clock();
+ break;
+ default:
+ break;
+ }
+
+ num_called++;
}
+CLOCKSOURCE_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
+CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer-osc", dw_apb_timer_init);
#include <linux/io.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/platform_data/clocksource-nomadik-mtu.h>
+ #include <linux/sched_clock.h>
#include <asm/mach/time.h>
- #include <asm/sched_clock.h>
/*
* The MTU device hosts four different counters, with 4 set of
.dev_id = &nmdk_clkevt,
};
-void __init nmdk_timer_init(void __iomem *base, int irq)
+static void __init __nmdk_timer_init(void __iomem *base, int irq,
+ struct clk *pclk, struct clk *clk)
{
unsigned long rate;
- struct clk *clk0, *pclk0;
mtu_base = base;
- pclk0 = clk_get_sys("mtu0", "apb_pclk");
- BUG_ON(IS_ERR(pclk0));
- BUG_ON(clk_prepare(pclk0) < 0);
- BUG_ON(clk_enable(pclk0) < 0);
-
- clk0 = clk_get_sys("mtu0", NULL);
- BUG_ON(IS_ERR(clk0));
- BUG_ON(clk_prepare(clk0) < 0);
- BUG_ON(clk_enable(clk0) < 0);
+ BUG_ON(clk_prepare_enable(pclk));
+ BUG_ON(clk_prepare_enable(clk));
/*
* Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
* to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
* with 16 gives too low timer resolution.
*/
- rate = clk_get_rate(clk0);
+ rate = clk_get_rate(clk);
if (rate > 32000000) {
rate /= 16;
clk_prescale = MTU_CRn_PRESCALE_16;
mtu_delay_timer.freq = rate;
register_current_timer_delay(&mtu_delay_timer);
}
+
+void __init nmdk_timer_init(void __iomem *base, int irq)
+{
+ struct clk *clk0, *pclk0;
+
+ pclk0 = clk_get_sys("mtu0", "apb_pclk");
+ BUG_ON(IS_ERR(pclk0));
+ clk0 = clk_get_sys("mtu0", NULL);
+ BUG_ON(IS_ERR(clk0));
+
+ __nmdk_timer_init(base, irq, pclk0, clk0);
+}
+
+static void __init nmdk_timer_of_init(struct device_node *node)
+{
+ struct clk *pclk;
+ struct clk *clk;
+ void __iomem *base;
+ int irq;
+
+ base = of_iomap(node, 0);
+ if (!base)
+ panic("Can't remap registers");
+
+ pclk = of_clk_get_by_name(node, "apb_pclk");
+ if (IS_ERR(pclk))
+ panic("could not get apb_pclk");
+
+ clk = of_clk_get_by_name(node, "timclk");
+ if (IS_ERR(clk))
+ panic("could not get timclk");
+
+ irq = irq_of_parse_and_map(node, 0);
+ if (irq <= 0)
+ panic("Can't parse IRQ");
+
+ __nmdk_timer_init(base, irq, pclk, clk);
+}
+CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
+ nmdk_timer_of_init);
/*
* Handle extern requests for shutdown, reboot and sysrq
*/
+
+#define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt
+
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/slab.h>
void (*post)(int cancelled);
};
+#ifdef CONFIG_HIBERNATE_CALLBACKS
static void xen_hvm_post_suspend(int cancelled)
{
xen_arch_hvm_post_suspend(cancelled);
xen_mm_unpin_all();
}
-#ifdef CONFIG_HIBERNATE_CALLBACKS
static int xen_suspend(void *data)
{
struct suspend_info *si = data;
err = syscore_suspend();
if (err) {
- printk(KERN_ERR "xen_suspend: system core suspend failed: %d\n",
- err);
+ pr_err("%s: system core suspend failed: %d\n", __func__, err);
return err;
}
during suspend. */
err = freeze_processes();
if (err) {
- printk(KERN_ERR "xen suspend: freeze failed %d\n", err);
+ pr_err("%s: freeze failed %d\n", __func__, err);
goto out;
}
#endif
err = dpm_suspend_start(PMSG_FREEZE);
if (err) {
- printk(KERN_ERR "xen suspend: dpm_suspend_start %d\n", err);
+ pr_err("%s: dpm_suspend_start %d\n", __func__, err);
goto out_thaw;
}
err = dpm_suspend_end(PMSG_FREEZE);
if (err) {
- printk(KERN_ERR "dpm_suspend_end failed: %d\n", err);
+ pr_err("dpm_suspend_end failed: %d\n", err);
si.cancelled = 0;
goto out_resume;
}
dpm_resume_start(si.cancelled ? PMSG_THAW : PMSG_RESTORE);
if (err) {
- printk(KERN_ERR "failed to start xen_suspend: %d\n", err);
+ pr_err("failed to start xen_suspend: %d\n", err);
si.cancelled = 1;
}
dpm_resume_end(si.cancelled ? PMSG_THAW : PMSG_RESTORE);
- /* Make sure timer events get retriggered on all CPUs */
- clock_was_set();
-
out_thaw:
#ifdef CONFIG_PREEMPT
thaw_processes();
if (handler->cb) {
handler->cb();
} else {
- printk(KERN_INFO "Ignoring shutdown request: %s\n", str);
+ pr_info("Ignoring shutdown request: %s\n", str);
shutting_down = SHUTDOWN_INVALID;
}
if (err)
return;
if (!xenbus_scanf(xbt, "control", "sysrq", "%c", &sysrq_key)) {
- printk(KERN_ERR "Unable to read sysrq code in "
- "control/sysrq\n");
+ pr_err("Unable to read sysrq code in control/sysrq\n");
xenbus_transaction_end(xbt, 1);
return;
}
err = register_xenbus_watch(&shutdown_watch);
if (err) {
- printk(KERN_ERR "Failed to set shutdown watcher\n");
+ pr_err("Failed to set shutdown watcher\n");
return err;
}
#ifdef CONFIG_MAGIC_SYSRQ
err = register_xenbus_watch(&sysrq_watch);
if (err) {
- printk(KERN_ERR "Failed to set sysrq watcher\n");
+ pr_err("Failed to set sysrq watcher\n");
return err;
}
#endif
void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs);
void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs);
cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs);
- void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs);
-extern void dw_apb_timer_init(void);
#endif /* __DW_APB_TIMER_H__ */
typedef struct {
efi_table_hdr_t hdr;
- unsigned long get_time;
- unsigned long set_time;
- unsigned long get_wakeup_time;
- unsigned long set_wakeup_time;
- unsigned long set_virtual_address_map;
- unsigned long convert_pointer;
- unsigned long get_variable;
- unsigned long get_next_variable;
- unsigned long set_variable;
- unsigned long get_next_high_mono_count;
- unsigned long reset_system;
- unsigned long update_capsule;
- unsigned long query_capsule_caps;
- unsigned long query_variable_info;
+ void *get_time;
+ void *set_time;
+ void *get_wakeup_time;
+ void *set_wakeup_time;
+ void *set_virtual_address_map;
+ void *convert_pointer;
+ void *get_variable;
+ void *get_next_variable;
+ void *set_variable;
+ void *get_next_high_mono_count;
+ void *reset_system;
+ void *update_capsule;
+ void *query_capsule_caps;
+ void *query_variable_info;
} efi_runtime_services_t;
typedef efi_status_t efi_get_time_t (efi_time_t *tm, efi_time_cap_t *tc);
extern int __init efi_uart_console_only (void);
extern void efi_initialize_iomem_resources(struct resource *code_resource,
struct resource *data_resource, struct resource *bss_resource);
- extern unsigned long efi_get_time(void);
- extern int efi_set_rtc_mmss(unsigned long nowtime);
+ extern void efi_get_time(struct timespec *now);
+ extern int efi_set_rtc_mmss(const struct timespec *now);
extern void efi_reserve_boot_services(void);
extern struct efi_memory_map memmap;
need to set this unless you want the configured kernel build
directory to select the cross-compiler automatically.
+config COMPILE_TEST
+ bool "Compile also drivers which will not load"
+ default n
+ help
+ Some drivers can be compiled on a different platform than they are
+ intended to be run on. Despite they cannot be loaded there (or even
+ when they load they cannot be used due to missing HW support),
+ developers still, opposing to distributors, might want to build such
+ drivers to compile-test them.
+
+ If you are a developer and want to build everything available, say Y
+ here. If you are a user/distributor, say N here to exclude useless
+ drivers to be distributed.
+
config LOCALVERSION
string "Local version - append to kernel release"
help
is not required. This option greatly reduces the
memory footprint of RCU.
-config TINY_PREEMPT_RCU
- bool "Preemptible UP-only small-memory-footprint RCU"
- depends on PREEMPT && !SMP
- help
- This option selects the RCU implementation that is designed
- for real-time UP systems. This option greatly reduces the
- memory footprint of RCU.
-
endchoice
config PREEMPT_RCU
- def_bool ( TREE_PREEMPT_RCU || TINY_PREEMPT_RCU )
+ def_bool TREE_PREEMPT_RCU
help
This option enables preemptible-RCU code that is common between
the TREE_PREEMPT_RCU and TINY_PREEMPT_RCU implementations.
Accept the default if unsure.
config RCU_NOCB_CPU
- bool "Offload RCU callback processing from boot-selected CPUs (EXPERIMENTAL"
+ bool "Offload RCU callback processing from boot-selected CPUs"
depends on TREE_RCU || TREE_PREEMPT_RCU
default n
help
prompt "Build-forced no-CBs CPUs"
default RCU_NOCB_CPU_NONE
help
- This option allows no-CBs CPUs to be specified at build time.
- Additional no-CBs CPUs may be specified by the rcu_nocbs=
- boot parameter.
+ This option allows no-CBs CPUs (whose RCU callbacks are invoked
+ from kthreads rather than from softirq context) to be specified
+ at build time. Additional no-CBs CPUs may be specified by
+ the rcu_nocbs= boot parameter.
config RCU_NOCB_CPU_NONE
bool "No build_forced no-CBs CPUs"
help
This option does not force any of the CPUs to be no-CBs CPUs.
Only CPUs designated by the rcu_nocbs= boot parameter will be
- no-CBs CPUs.
+ no-CBs CPUs, whose RCU callbacks will be invoked by per-CPU
+ kthreads whose names begin with "rcuo". All other CPUs will
+ invoke their own RCU callbacks in softirq context.
+
+ Select this option if you want to choose no-CBs CPUs at
+ boot time, for example, to allow testing of different no-CBs
+ configurations without having to rebuild the kernel each time.
config RCU_NOCB_CPU_ZERO
bool "CPU 0 is a build_forced no-CBs CPU"
depends on RCU_NOCB_CPU && !NO_HZ_FULL
help
- This option forces CPU 0 to be a no-CBs CPU. Additional CPUs
- may be designated as no-CBs CPUs using the rcu_nocbs= boot
- parameter will be no-CBs CPUs.
+ This option forces CPU 0 to be a no-CBs CPU, so that its RCU
+ callbacks are invoked by a per-CPU kthread whose name begins
+ with "rcuo". Additional CPUs may be designated as no-CBs
+ CPUs using the rcu_nocbs= boot parameter will be no-CBs CPUs.
+ All other CPUs will invoke their own RCU callbacks in softirq
+ context.
Select this if CPU 0 needs to be a no-CBs CPU for real-time
- or energy-efficiency reasons.
+ or energy-efficiency reasons, but the real reason it exists
+ is to ensure that randconfig testing covers mixed systems.
config RCU_NOCB_CPU_ALL
bool "All CPUs are build_forced no-CBs CPUs"
depends on RCU_NOCB_CPU
help
This option forces all CPUs to be no-CBs CPUs. The rcu_nocbs=
- boot parameter will be ignored.
+ boot parameter will be ignored. All CPUs' RCU callbacks will
+ be executed in the context of per-CPU rcuo kthreads created for
+ this purpose. Assuming that the kthreads whose names start with
+ "rcuo" are bound to "housekeeping" CPUs, this reduces OS jitter
+ on the remaining CPUs, but might decrease memory locality during
+ RCU-callback invocation, thus potentially degrading throughput.
Select this if all CPUs need to be no-CBs CPUs for real-time
or energy-efficiency reasons.
config HAVE_UNSTABLE_SCHED_CLOCK
bool
+ config GENERIC_SCHED_CLOCK
+ bool
+
#
# For architectures that want to enable the support for NUMA-affine scheduler
# balancing logic:
Note that setting this option increases fixed memory overhead
associated with each page of memory in the system. By this,
- 20(40)bytes/PAGE_SIZE on 32(64)bit system will be occupied by memory
+ 8(16)bytes/PAGE_SIZE on 32(64)bit system will be occupied by memory
usage tracking struct at boot. Total amount of this is printed out
at boot.
the unaligned access emulation.
see arch/parisc/kernel/unaligned.c for reference
-config HOTPLUG
- def_bool y
-
config HAVE_PCSPKR_PLATFORM
bool
#include <linux/ptrace.h>
#include <linux/blkdev.h>
#include <linux/elevator.h>
+ #include <linux/sched_clock.h>
#include <asm/io.h>
#include <asm/bugs.h>
if (WARN(!irqs_disabled(), "Interrupts were enabled *very* early, fixing it\n"))
local_irq_disable();
idr_init_cache();
- perf_event_init();
rcu_init();
tick_nohz_init();
radix_tree_init();
softirq_init();
timekeeping_init();
time_init();
+ sched_clock_postinit();
+ perf_event_init();
profile_init();
call_function_init();
WARN(!irqs_disabled(), "Interrupts were enabled early\n");
bool initcall_debug;
core_param(initcall_debug, initcall_debug, bool, 0644);
-static char msgbuf[64];
-
static int __init_or_module do_one_initcall_debug(initcall_t fn)
{
ktime_t calltime, delta, rettime;
{
int count = preempt_count();
int ret;
+ char msgbuf[64];
if (initcall_debug)
ret = do_one_initcall_debug(fn);
#include <linux/sched/sysctl.h>
#include <linux/sched/rt.h>
#include <linux/timer.h>
+#include <linux/freezer.h>
#include <asm/uaccess.h>
return 1;
}
+ static void clock_was_set_work(struct work_struct *work)
+ {
+ clock_was_set();
+ }
+
+ static DECLARE_WORK(hrtimer_work, clock_was_set_work);
+
/*
- * Called from timekeeping code to reprogramm the hrtimer interrupt
- * device. If called from the timer interrupt context we defer it to
- * softirq context.
+ * Called from timekeeping and resume code to reprogramm the hrtimer
+ * interrupt device on all cpus.
*/
void clock_was_set_delayed(void)
{
- struct hrtimer_cpu_base *cpu_base = &__get_cpu_var(hrtimer_bases);
-
- cpu_base->clock_was_set = 1;
- __raise_softirq_irqoff(HRTIMER_SOFTIRQ);
+ schedule_work(&hrtimer_work);
}
#else
/*
* During resume we might have to reprogram the high resolution timer
- * interrupt (on the local CPU):
+ * interrupt on all online CPUs. However, all other CPUs will be
+ * stopped with IRQs interrupts disabled so the clock_was_set() call
+ * must be deferred.
*/
void hrtimers_resume(void)
{
WARN_ONCE(!irqs_disabled(),
KERN_INFO "hrtimers_resume() called with IRQs enabled!");
+ /* Retrigger on the local CPU */
retrigger_next_event(NULL);
- timerfd_clock_was_set();
+ /* And schedule a retrigger for all others */
+ clock_was_set_delayed();
}
static inline void timer_stats_hrtimer_set_start_info(struct hrtimer *timer)
static void run_hrtimer_softirq(struct softirq_action *h)
{
- struct hrtimer_cpu_base *cpu_base = &__get_cpu_var(hrtimer_bases);
-
- if (cpu_base->clock_was_set) {
- cpu_base->clock_was_set = 0;
- clock_was_set();
- }
-
hrtimer_peek_ahead_timers();
}
t->task = NULL;
if (likely(t->task))
- schedule();
+ freezable_schedule();
hrtimer_cancel(&t->timer);
mode = HRTIMER_MODE_ABS;
*/
static inline void sched_info_dequeued(struct task_struct *t)
{
- unsigned long long now = task_rq(t)->clock, delta = 0;
+ unsigned long long now = rq_clock(task_rq(t)), delta = 0;
if (unlikely(sched_info_on()))
if (t->sched_info.last_queued)
*/
static void sched_info_arrive(struct task_struct *t)
{
- unsigned long long now = task_rq(t)->clock, delta = 0;
+ unsigned long long now = rq_clock(task_rq(t)), delta = 0;
if (t->sched_info.last_queued)
delta = now - t->sched_info.last_queued;
{
if (unlikely(sched_info_on()))
if (!t->sched_info.last_queued)
- t->sched_info.last_queued = task_rq(t)->clock;
+ t->sched_info.last_queued = rq_clock(task_rq(t));
}
/*
*/
static inline void sched_info_depart(struct task_struct *t)
{
- unsigned long long delta = task_rq(t)->clock -
+ unsigned long long delta = rq_clock(task_rq(t)) -
t->sched_info.last_arrival;
rq_sched_info_depart(task_rq(t), delta);
* on CONFIG_SCHEDSTATS.
*/
+ /**
+ * cputimer_running - return true if cputimer is running
+ *
+ * @tsk: Pointer to target task.
+ */
+ static inline bool cputimer_running(struct task_struct *tsk)
+
+ {
+ struct thread_group_cputimer *cputimer = &tsk->signal->cputimer;
+
+ if (!cputimer->running)
+ return false;
+
+ /*
+ * After we flush the task's sum_exec_runtime to sig->sum_sched_runtime
+ * in __exit_signal(), we won't account to the signal struct further
+ * cputime consumed by that task, even though the task can still be
+ * ticking after __exit_signal().
+ *
+ * In order to keep a consistent behaviour between thread group cputime
+ * and thread group cputimer accounting, lets also ignore the cputime
+ * elapsing after __exit_signal() in any thread group timer running.
+ *
+ * This makes sure that POSIX CPU clocks and timers are synchronized, so
+ * that a POSIX CPU timer won't expire while the corresponding POSIX CPU
+ * clock delta is behind the expiring timer value.
+ */
+ if (unlikely(!tsk->sighand))
+ return false;
+
+ return true;
+ }
+
/**
* account_group_user_time - Maintain utime for a thread group.
*
{
struct thread_group_cputimer *cputimer = &tsk->signal->cputimer;
- if (!cputimer->running)
+ if (!cputimer_running(tsk))
return;
raw_spin_lock(&cputimer->lock);
{
struct thread_group_cputimer *cputimer = &tsk->signal->cputimer;
- if (!cputimer->running)
+ if (!cputimer_running(tsk))
return;
raw_spin_lock(&cputimer->lock);
{
struct thread_group_cputimer *cputimer = &tsk->signal->cputimer;
- if (!cputimer->running)
+ if (!cputimer_running(tsk))
return;
raw_spin_lock(&cputimer->lock);
git.openpandora.org / pandora-kernel.git / commitdiff