if ((be.major == 0xff) && (be.minor == 0xff))
return MPC85XX_CPU_BOARD_REV(0, 0);
- return MPC85XX_CPU_BOARD_REV(e.major, e.minor);
+ return MPC85XX_CPU_BOARD_REV(be.major, be.minor);
}
#endif
volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
return -1;
}
}
- im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CFG_DDR_SIZE != 256)
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
- im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff;
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
/* Only one CS0 for DDR */
im->ddr.csbnds[0].csbnds = 0x0000000f;
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
#if (CFG_DDR_SIZE != 512)
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
if (ddr_size & 1)
return -1;
}
- im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
LAWAR_SIZE);
return -1;
}
}
- im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CFG_DDR_SIZE != 256)
/*
* Set up LAWBAR for all of DDR.
*/
- ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ ecm->bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
debug("DDR:bar=0x%08x\n", ecm->bar);
debug("DDR:ar=0x%08x\n", ecm->ar);
struct cpu_type *cpu;
#ifdef CONFIG_DDR_CLK_FREQ
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+ >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
#endif
}
fdt_setprop(blob, off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
- fdt_setprop_cell(blob, off, "cache-line-size", line_size);
fdt_setprop_cell(blob, off, "cache-size", size);
fdt_setprop_cell(blob, off, "cache-sets", num_sets);
fdt_setprop_cell(blob, off, "cache-level", 2);
dnum_sets = dsize / (dline_size * dnum_ways);
fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
- fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size);
fdt_setprop_cell(blob, off, "d-cache-size", dsize);
fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
inum_sets = isize / (iline_size * inum_ways);
fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
- fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size);
fdt_setprop_cell(blob, off, "i-cache-size", isize);
fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
#ifdef CONFIG_DDR_CLK_FREQ
{
- u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+ >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
if (ddr_ratio != 0x7)
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
*/
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
- gd->i2c1_clk = sys_info.freqSystemBus / 3;
- else
gd->i2c1_clk = sys_info.freqSystemBus / 2;
+ else
+ gd->i2c1_clk = sys_info.freqSystemBus / 3;
#else
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
gd->i2c1_clk = sys_info.freqSystemBus / 2;
/* XXX - Need to test on x8/x16 in parallel. */
info->portwidth >>= 1;
}
+
+ flash_write_cmd (info, 0, 0, info->cmd_reset);
}
- flash_write_cmd (info, 0, 0, info->cmd_reset);
return (info->size);
}
*/
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
+#ifdef CONFIG_MPC8536
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
+#else
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
+#endif
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CFG_FLASH_SIZE 8 /* flash size in MB */
+#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
#define CONFIG_FDTFILE mpc8313erdb.dtb
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define XMK_STR(x) #x
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 8 /* FLASH size is 8M */
+#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
+#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
#define CONFIG_FDTFILE mpc832x_rdb.dtb
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define XMK_STR(x) #x
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
+#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CFG_FLASH_SIZE 32 /* max flash size in MB */
+#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
/* #define CFG_FLASH_USE_BUFFER_WRITE */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
#define CFG_FLASH_SIZE 16 /* FLASH size in MB */
#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
+#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
/* Vitesse 7385 */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
+#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
+#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */
+#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
#define CONFIG_FDTFILE mpc8379_rdb.dtb
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define XMK_STR(x) #x
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
-/* #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /\* ddrclk for MPC85xx *\/ FIXME-8536*/
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
from ICS307 instead of switches */
*/
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
-#define CONFIG_ID_EEPROM
#define CFG_I2C_EEPROM_NXID
#endif
#define CFG_I2C_EEPROM_ADDR 0x57
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
/* I2C addresses of SPD EEPROMs */
+#define CFG_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CFG_I2C_OFFSET 0x3100
+#define CFG_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CFG_I2C_EEPROM_NXID
+#endif
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_BUS_NUM 1
/*
* General PCI
/* Low-level functions (you probably don't need these) */
/**********************************************************************/
-const void *fdt_offset_ptr(const void *fdt, int offset, int checklen);
+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
{
return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
*/
uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
+/**
+ * fdt_get_alias_namelen - get alias based on substring
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias th look up
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_get_alias(), but only examine the first namelen
+ * characters of name for matching the alias name.
+ */
+const char *fdt_get_alias_namelen(const void *fdt,
+ const char *name, int namelen);
+
+/**
+ * fdt_get_alias - retreive the path referenced by a given alias
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias th look up
+ *
+ * fdt_get_alias() retrieves the value of a given alias. That is, the
+ * value of the property named 'name' in the node /aliases.
+ *
+ * returns:
+ * a pointer to the expansion of the alias named 'name', of it exists
+ * NULL, if the given alias or the /aliases node does not exist
+ */
+const char *fdt_get_alias(const void *fdt, const char *name);
+
/**
* fdt_get_path - determine the full path of a node
* @fdt: pointer to the device tree blob
#if defined(CONFIG_MPC834X)
#define HRCWH_ROM_LOC_PCI2 0x00200000
#endif
-#if defined(CONIFG_MPC837X)
+#if defined(CONFIG_MPC837X)
#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
* if the user wants it (the logic is in the subroutines).
*/
if (of_size) {
- if (fdt_chosen(of_flat_tree, 0) < 0) {
+ if (fdt_chosen(of_flat_tree, 1) < 0) {
puts ("ERROR: ");
puts ("/chosen node create failed");
puts (" - must RESET the board to recover.\n");
return 0;
}
-const void *fdt_offset_ptr(const void *fdt, int offset, int len)
+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len)
{
const char *p;
/* see if we have an alias */
if (*path != '/') {
- const char *q;
- int aliasoffset = fdt_path_offset(fdt, "/aliases");
-
- if (aliasoffset < 0)
- return -FDT_ERR_BADPATH;
+ const char *q = strchr(path, '/');
- q = strchr(path, '/');
if (!q)
q = end;
- p = fdt_getprop_namelen(fdt, aliasoffset, path, q - p, NULL);
+ p = fdt_get_alias_namelen(fdt, p, q - p);
if (!p)
return -FDT_ERR_BADPATH;
offset = fdt_path_offset(fdt, p);
return fdt32_to_cpu(*php);
}
+const char *fdt_get_alias_namelen(const void *fdt,
+ const char *name, int namelen)
+{
+ int aliasoffset;
+
+ aliasoffset = fdt_path_offset(fdt, "/aliases");
+ if (aliasoffset < 0)
+ return NULL;
+
+ return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL);
+}
+
+const char *fdt_get_alias(const void *fdt, const char *name)
+{
+ return fdt_get_alias_namelen(fdt, name, strlen(name));
+}
+
int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
{
int pdepth = 0, p = 0;
for (offset = 0, depth = 0;
(offset >= 0) && (offset <= nodeoffset);
offset = fdt_next_node(fdt, offset, &depth)) {
- if (pdepth < depth)
- continue; /* overflowed buffer */
-
while (pdepth > depth) {
do {
p--;
pdepth--;
}
- name = fdt_get_name(fdt, offset, &namelen);
- if (!name)
- return namelen;
- if ((p + namelen + 1) <= buflen) {
- memcpy(buf + p, name, namelen);
- p += namelen;
- buf[p++] = '/';
- pdepth++;
+ if (pdepth >= depth) {
+ name = fdt_get_name(fdt, offset, &namelen);
+ if (!name)
+ return namelen;
+ if ((p + namelen + 1) <= buflen) {
+ memcpy(buf + p, name, namelen);
+ p += namelen;
+ buf[p++] = '/';
+ pdepth++;
+ }
}
if (offset == nodeoffset) {
if (p > 1) /* special case so that root path is "/", not "" */
p--;
buf[p] = '\0';
- return p;
+ return 0;
}
}
git.openpandora.org / pandora-u-boot.git / commitdiff