Documentation: Add documentation for the APM X-Gene SoC SATA host controller DTS...

This patch adds documentation for the APM X-Gene SoC SATA host controller DTS
binding.

Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Tejun Heo <tj@kernel.org>

diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt
new file mode 100644 (file)
index 0000000..7bcfbf5
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt
@@ -0,0 +1,76 @@
+* APM X-Gene 6.0 Gb/s SATA host controller nodes
+
+SATA host controller nodes are defined to describe on-chip Serial ATA
+controllers. Each SATA controller (pair of ports) have its own node.
+
+Required properties:
+- compatible           : Shall contain:
+  * "apm,xgene-ahci"
+- reg                  : First memory resource shall be the AHCI memory
+                         resource.
+                         Second memory resource shall be the host controller
+                         core memory resource.
+                         Third memory resource shall be the host controller
+                         diagnostic memory resource.
+                         4th memory resource shall be the host controller
+                         AXI memory resource.
+                         5th optional memory resource shall be the host
+                         controller MUX memory resource if required.
+- interrupts           : Interrupt-specifier for SATA host controller IRQ.
+- clocks               : Reference to the clock entry.
+- phys                 : A list of phandles + phy-specifiers, one for each
+                         entry in phy-names.
+- phy-names            : Should contain:
+  * "sata-phy" for the SATA 6.0Gbps PHY
+
+Optional properties:
+- status               : Shall be "ok" if enabled or "disabled" if disabled.
+                         Default is "ok".
+
+Example:
+               sataclk: sataclk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <1>;
+                       clock-frequency = <100000000>;
+                       clock-output-names = "sataclk";
+               };
+
+               phy2: phy@1f22a000 {
+                       compatible = "apm,xgene-phy";
+                       reg = <0x0 0x1f22a000 0x0 0x100>;
+                       #phy-cells = <1>;
+               };
+
+               phy3: phy@1f23a000 {
+                       compatible = "apm,xgene-phy";
+                       reg = <0x0 0x1f23a000 0x0 0x100>;
+                       #phy-cells = <1>;
+               };
+
+               sata2: sata@1a400000 {
+                       compatible = "apm,xgene-ahci";
+                       reg = <0x0 0x1a400000 0x0 0x1000>,
+                             <0x0 0x1f220000 0x0 0x1000>,
+                             <0x0 0x1f22d000 0x0 0x1000>,
+                             <0x0 0x1f22e000 0x0 0x1000>,
+                             <0x0 0x1f227000 0x0 0x1000>;
+                       interrupts = <0x0 0x87 0x4>;
+                       status = "ok";
+                       clocks = <&sataclk 0>;
+                       phys = <&phy2 0>;
+                       phy-names = "sata-phy";
+               };
+
+               sata3: sata@1a800000 {
+                       compatible = "apm,xgene-ahci-pcie";
+                       reg = <0x0 0x1a800000 0x0 0x1000>,
+                             <0x0 0x1f230000 0x0 0x1000>,
+                             <0x0 0x1f23d000 0x0 0x1000>,
+                             <0x0 0x1f23e000 0x0 0x1000>,
+                             <0x0 0x1f237000 0x0 0x1000>;
+                       interrupts = <0x0 0x88 0x4>;
+                       status = "ok";
+                       clocks = <&sataclk 0>;
+                       phys = <&phy3 0>;
+                       phy-names = "sata-phy";
+               };