ioat2,3: cacheline align software descriptor allocations

All the necessary fields for handling an ioat2,3 ring entry can fit into
one cacheline.  Move ->len prior to ->txd in struct ioat_ring_ent, and
move allocation of these entries to a hw-cache-aligned kmem cache to
reduce the number of cachelines dirtied for descriptor management.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --cc drivers/dma/ioat/dma_v2.c
Simple merge

diff --cc drivers/dma/ioat/dma_v2.h
Simple merge

diff --cc drivers/dma/ioat/pci.c
Simple merge