phy-names = "dp-phy0";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
-};
-&out_dp {
- dpsub_dp_out: endpoint {
- remote-endpoint = <&dpcon_in>;
+ ports {
+ out_dp: port@5 {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+ };
};
};
phy-names = "dp-phy0";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
-};
-&out_dp {
- dpsub_dp_out: endpoint {
- remote-endpoint = <&dpcon_in>;
+ ports {
+ out_dp: port@5 {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+ };
};
};
* dts file for KV260 revA Carrier Card
*
* (C) Copyright 2020 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
*
* SD level shifter:
* "A" - A01 board un-modified (NXP)
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
-};
-&out_dp {
- dpsub_dp_out: endpoint {
- remote-endpoint = <&dpcon_in>;
+ ports {
+ out_dp: port@5 {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+ };
};
};
* dts file for KV260 revA Carrier Card
*
* (C) Copyright 2020 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
-};
-&out_dp {
- dpsub_dp_out: endpoint {
- remote-endpoint = <&dpcon_in>;
+ ports {
+ out_dp: port@5 {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+ };
};
};