[PATCH] x86_64: Some housekeeping in local APIC code

Remove support for obsolete hardware and cleanup.

- Remove checks for non integrated APICs
- Replace apic_write_around with apic_write.
- Remove apic_read_around
- Remove APIC version reads used by old workarounds
- Remove old workaround for Simics
- Fix indentation

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/arch/x86_64/kernel/apic.c b/arch/x86_64/kernel/apic.c
index c3239f6..8fdd089 100644 (file)
--- a/arch/x86_64/kernel/apic.c
+++ b/arch/x86_64/kernel/apic.c
@@ -53,20 +53,17 @@ static void apic_pm_activate(void);
 
 void enable_NMI_through_LVT0 (void * dummy)
 {
-       unsigned int v, ver;
+       unsigned int v;
        
-       ver = apic_read(APIC_LVR);
-       ver = GET_APIC_VERSION(ver);
        v = APIC_DM_NMI;                        /* unmask and set to NMI */
-       apic_write_around(APIC_LVT0, v);
+       apic_write(APIC_LVT0, v);
 }
 
 int get_maxlvt(void)
 {
-       unsigned int v, ver, maxlvt;
+       unsigned int v, maxlvt;
 
        v = apic_read(APIC_LVR);
-       ver = GET_APIC_VERSION(v);
        maxlvt = GET_APIC_MAXLVT(v);
        return maxlvt;
 }
@@ -84,33 +81,33 @@ void clear_local_APIC(void)
         */
        if (maxlvt >= 3) {
                v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
-               apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
+               apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
        }
        /*
         * Careful: we have to set masks only first to deassert
         * any level-triggered sources.
         */
        v = apic_read(APIC_LVTT);
-       apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
+       apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
        v = apic_read(APIC_LVT0);
-       apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
+       apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
        v = apic_read(APIC_LVT1);
-       apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
+       apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
        if (maxlvt >= 4) {
                v = apic_read(APIC_LVTPC);
-               apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
+               apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
        }
 
        /*
         * Clean APIC state for other OSs:
         */
-       apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
-       apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
-       apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
+       apic_write(APIC_LVTT, APIC_LVT_MASKED);
+       apic_write(APIC_LVT0, APIC_LVT_MASKED);
+       apic_write(APIC_LVT1, APIC_LVT_MASKED);
        if (maxlvt >= 3)
-               apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
+               apic_write(APIC_LVTERR, APIC_LVT_MASKED);
        if (maxlvt >= 4)
-               apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
+               apic_write(APIC_LVTPC, APIC_LVT_MASKED);
        v = GET_APIC_VERSION(apic_read(APIC_LVR));
        apic_write(APIC_ESR, 0);
        apic_read(APIC_ESR);
@@ -155,7 +152,7 @@ void disconnect_bsp_APIC(int virt_wire_setup)
                value &= ~APIC_VECTOR_MASK;
                value |= APIC_SPIV_APIC_ENABLED;
                value |= 0xf;
-               apic_write_around(APIC_SPIV, value);
+               apic_write(APIC_SPIV, value);
 
                if (!virt_wire_setup) {
                        /* For LVT0 make it edge triggered, active high, external and enabled */
@@ -165,11 +162,11 @@ void disconnect_bsp_APIC(int virt_wire_setup)
                                APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
                        value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
                        value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
-                       apic_write_around(APIC_LVT0, value);
+                       apic_write(APIC_LVT0, value);
                }
                else {
                        /* Disable LVT0 */
-                       apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
+                       apic_write(APIC_LVT0, APIC_LVT_MASKED);
                }
 
                /* For LVT1 make it edge triggered, active high, nmi and enabled */
@@ -180,7 +177,7 @@ void disconnect_bsp_APIC(int virt_wire_setup)
                        APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
                value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
                value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
-               apic_write_around(APIC_LVT1, value);
+               apic_write(APIC_LVT1, value);
        }
 }
 
@@ -196,7 +193,7 @@ void disable_local_APIC(void)
         */
        value = apic_read(APIC_SPIV);
        value &= ~APIC_SPIV_APIC_ENABLED;
-       apic_write_around(APIC_SPIV, value);
+       apic_write(APIC_SPIV, value);
 }
 
 /*
@@ -273,7 +270,7 @@ void __init sync_Arb_IDs(void)
        apic_wait_icr_idle();
 
        apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
-       apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
+       apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
                                | APIC_DM_INIT);
 }
 
@@ -284,7 +281,7 @@ extern void __error_in_apic_c (void);
  */
 void __init init_bsp_APIC(void)
 {
-       unsigned int value, ver;
+       unsigned int value;
 
        /*
         * Don't do the setup now if we have a SMP BIOS as the
@@ -294,7 +291,6 @@ void __init init_bsp_APIC(void)
                return;
 
        value = apic_read(APIC_LVR);
-       ver = GET_APIC_VERSION(value);
 
        /*
         * Do not trust the local APIC being empty at bootup.
@@ -309,22 +305,21 @@ void __init init_bsp_APIC(void)
        value |= APIC_SPIV_APIC_ENABLED;
        value |= APIC_SPIV_FOCUS_DISABLED;
        value |= SPURIOUS_APIC_VECTOR;
-       apic_write_around(APIC_SPIV, value);
+       apic_write(APIC_SPIV, value);
 
        /*
         * Set up the virtual wire mode.
         */
-       apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
+       apic_write(APIC_LVT0, APIC_DM_EXTINT);
        value = APIC_DM_NMI;
-       apic_write_around(APIC_LVT1, value);
+       apic_write(APIC_LVT1, value);
 }
 
 void __cpuinit setup_local_APIC (void)
 {
-       unsigned int value, ver, maxlvt;
+       unsigned int value, maxlvt;
 
        value = apic_read(APIC_LVR);
-       ver = GET_APIC_VERSION(value);
 
        if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
                __error_in_apic_c();
@@ -349,7 +344,7 @@ void __cpuinit setup_local_APIC (void)
         */
        value = apic_read(APIC_TASKPRI);
        value &= ~APIC_TPRI_MASK;
-       apic_write_around(APIC_TASKPRI, value);
+       apic_write(APIC_TASKPRI, value);
 
        /*
         * Now that we are all set up, enable the APIC
@@ -391,7 +386,7 @@ void __cpuinit setup_local_APIC (void)
         * Set spurious IRQ vector
         */
        value |= SPURIOUS_APIC_VECTOR;
-       apic_write_around(APIC_SPIV, value);
+       apic_write(APIC_SPIV, value);
 
        /*
         * Set up LVT0, LVT1:
@@ -411,7 +406,7 @@ void __cpuinit setup_local_APIC (void)
                value = APIC_DM_EXTINT | APIC_LVT_MASKED;
                apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
        }
-       apic_write_around(APIC_LVT0, value);
+       apic_write(APIC_LVT0, value);
 
        /*
         * only the BP should see the LINT1 NMI signal, obviously.
@@ -420,14 +415,14 @@ void __cpuinit setup_local_APIC (void)
                value = APIC_DM_NMI;
        else
                value = APIC_DM_NMI | APIC_LVT_MASKED;
-       apic_write_around(APIC_LVT1, value);
+       apic_write(APIC_LVT1, value);
 
        {
                unsigned oldvalue;
                maxlvt = get_maxlvt();
                oldvalue = apic_read(APIC_ESR);
                value = ERROR_APIC_VECTOR;      // enables sending errors
-               apic_write_around(APIC_LVTERR, value);
+               apic_write(APIC_LVTERR, value);
                /*
                 * spec says clear errors after enabling vector.
                 */
@@ -672,17 +667,17 @@ static void __setup_APIC_LVTT(unsigned int clocks)
        if (cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask))
                lvtt_value |= APIC_LVT_MASKED;
 
-       apic_write_around(APIC_LVTT, lvtt_value);
+       apic_write(APIC_LVTT, lvtt_value);
 
        /*
         * Divide PICLK by 16
         */
        tmp_value = apic_read(APIC_TDCR);
-       apic_write_around(APIC_TDCR, (tmp_value
+       apic_write(APIC_TDCR, (tmp_value
                                & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
                                | APIC_TDR_DIV_16);
 
-       apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
+       apic_write(APIC_TMICT, clocks/APIC_DIVISOR);
 }
 
 static void setup_APIC_timer(unsigned int clocks)
@@ -691,12 +686,6 @@ static void setup_APIC_timer(unsigned int clocks)
 
        local_irq_save(flags);
 
-       /* For some reasons this doesn't work on Simics, so fake it for now */ 
-       if (!strstr(boot_cpu_data.x86_model_id, "Screwdriver")) { 
-       __setup_APIC_LVTT(clocks);
-               return;
-       } 
-
        /* wait for irq slice */
        if (vxtime.hpet_address) {
                int trigger = hpet_readl(HPET_T0_CMP);
@@ -709,7 +698,7 @@ static void setup_APIC_timer(unsigned int clocks)
                outb_p(0x00, 0x43);
                c2 = inb_p(0x40);
                c2 |= inb_p(0x40) << 8;
-       do {
+               do {
                        c1 = c2;
                        outb_p(0x00, 0x43);
                        c2 = inb_p(0x40);
@@ -800,7 +789,7 @@ void disable_APIC_timer(void)
                unsigned long v;
 
                v = apic_read(APIC_LVTT);
-               apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
+               apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
        }
 }
 
@@ -813,7 +802,7 @@ void enable_APIC_timer(void)
                unsigned long v;
 
                v = apic_read(APIC_LVTT);
-               apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
+               apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED);
        }
 }
 
@@ -1066,7 +1055,7 @@ int __init APIC_init_uniprocessor (void)
        connect_bsp_APIC();
 
        phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
-       apic_write_around(APIC_ID, SET_APIC_ID(boot_cpu_id));
+       apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
 
        setup_local_APIC();
 

diff --git a/arch/x86_64/kernel/io_apic.c b/arch/x86_64/kernel/io_apic.c
index fd1e7c3..e8cf44e 100644 (file)
--- a/arch/x86_64/kernel/io_apic.c
+++ b/arch/x86_64/kernel/io_apic.c
@@ -910,7 +910,7 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in
        disable_8259A_irq(0);
 
        /* mask LVT0 */
-       apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
+       apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 
        /*
         * We use logical delivery to get the timer IRQ
@@ -1635,7 +1635,7 @@ static void enable_lapic_irq (unsigned int irq)
        unsigned long v;
 
        v = apic_read(APIC_LVT0);
-       apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
+       apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
 }
 
 static void disable_lapic_irq (unsigned int irq)
@@ -1643,7 +1643,7 @@ static void disable_lapic_irq (unsigned int irq)
        unsigned long v;
 
        v = apic_read(APIC_LVT0);
-       apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
+       apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
 }
 
 static void ack_lapic_irq (unsigned int irq)
@@ -1769,7 +1769,7 @@ static inline void check_timer(void)
         * the 8259A which implies the virtual wire has to be
         * disabled in the local APIC.
         */
-       apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
+       apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
        init_8259A(1);
        enable_8259A_irq(0);
 
@@ -1835,21 +1835,21 @@ static inline void check_timer(void)
 
        disable_8259A_irq(0);
        irq_desc[0].handler = &lapic_irq_type;
-       apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
+       apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
        enable_8259A_irq(0);
 
        if (timer_irq_works()) {
                apic_printk(APIC_QUIET, " works.\n");
                return;
        }
-       apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
+       apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
        apic_printk(APIC_VERBOSE," failed.\n");
 
        apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
 
        init_8259A(0);
        make_8259A_irq(0);
-       apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
+       apic_write(APIC_LVT0, APIC_DM_EXTINT);
 
        unlock_ExtINT_logic();
 

diff --git a/arch/x86_64/kernel/mce_intel.c b/arch/x86_64/kernel/mce_intel.c
index 3ef845e..8f533d2 100644 (file)
--- a/arch/x86_64/kernel/mce_intel.c
+++ b/arch/x86_64/kernel/mce_intel.c
@@ -80,7 +80,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
 
        h = THERMAL_APIC_VECTOR;
        h |= (APIC_DM_FIXED | APIC_LVT_MASKED);
-       apic_write_around(APIC_LVTTHMR, h);
+       apic_write(APIC_LVTTHMR, h);
 
        rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
        wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
@@ -89,7 +89,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
        wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);
 
        l = apic_read(APIC_LVTTHMR);
-       apic_write_around(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
+       apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
        printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",
                cpu, tm2 ? "TM2" : "TM1");
        return;

diff --git a/arch/x86_64/kernel/smpboot.c b/arch/x86_64/kernel/smpboot.c
index c8169d0..c9e941a 100644 (file)
--- a/arch/x86_64/kernel/smpboot.c
+++ b/arch/x86_64/kernel/smpboot.c
@@ -666,7 +666,6 @@ static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int sta
 
        for (j = 1; j <= num_starts; j++) {
                Dprintk("Sending STARTUP #%d.\n",j);
-               apic_read_around(APIC_SPIV);
                apic_write(APIC_ESR, 0);
                apic_read(APIC_ESR);
                Dprintk("After apic_write.\n");
@@ -705,7 +704,6 @@ static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int sta
                 * Due to the Pentium erratum 3AP.
                 */
                if (maxlvt > 3) {
-                       apic_read_around(APIC_SPIV);
                        apic_write(APIC_ESR, 0);
                }
                accept_status = (apic_read(APIC_ESR) & 0xEF);
@@ -842,11 +840,8 @@ do_rest:
        /*
         * Be paranoid about clearing APIC errors.
         */
-       if (APIC_INTEGRATED(apic_version[apicid])) {
-               apic_read_around(APIC_SPIV);
-               apic_write(APIC_ESR, 0);
-               apic_read(APIC_ESR);
-       }
+       apic_write(APIC_ESR, 0);
+       apic_read(APIC_ESR);
 
        /*
         * Status is now clean
@@ -1024,7 +1019,7 @@ static int __init smp_sanity_check(unsigned max_cpus)
        /*
         * If we couldn't find a local APIC, then get out of here now!
         */
-       if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) {
+       if (!cpu_has_apic) {
                printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
                        boot_cpu_id);
                printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");

diff --git a/include/asm-x86_64/apic.h b/include/asm-x86_64/apic.h
index f95847a..4f6a4dc 100644 (file)
--- a/include/asm-x86_64/apic.h
+++ b/include/asm-x86_64/apic.h
@@ -52,10 +52,6 @@ static __inline__ void apic_wait_icr_idle(void)
        while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY );
 }
 
-#define FORCE_READ_AROUND_WRITE 0
-#define apic_read_around(x)
-#define apic_write_around(x,y) apic_write((x),(y))
-
 static inline void ack_APIC_irq(void)
 {
        /*
@@ -66,7 +62,7 @@ static inline void ack_APIC_irq(void)
         */
 
        /* Docs say use 0 for future compatibility */
-       apic_write_around(APIC_EOI, 0);
+       apic_write(APIC_EOI, 0);
 }
 
 extern int get_maxlvt (void);