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pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
authorPeter Rosin <peda@axentia.se>
Thu, 5 Feb 2015 06:02:09 +0000 (14:02 +0800)
committerNicolas Ferre <nicolas.ferre@atmel.com>
Tue, 3 Mar 2015 18:43:59 +0000 (19:43 +0100)
The DDRSDR controller fails miserably to put LPDDR1 memories in
self-refresh. Force the controller to think it has DDR2 memories
during the self-refresh period, as the DDR2 self-refresh spec is
equivalent to LPDDR1, and is correctly implemented in the
controller.

Assume that the second controller has the same fault, but that is
untested.

Signed-off-by: Peter Rosin <peda@axentia.se>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
arch/arm/mach-at91/pm_slowclock.S patch | blob | history
include/soc/at91/at91sam9_ddrsdr.h patch | blob | history

diff --cc arch/arm/mach-at91/pm_slowclock.S
Simple merge
diff --cc include/soc/at91/at91sam9_ddrsdr.h
Simple merge
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