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intel/iommu: force writebuffer-flush quirk on Gen 4 Chipsets
author
Daniel Vetter
<daniel.vetter@ffwll.ch>
Mon, 21 Jan 2013 18:48:59 +0000
(19:48 +0100)
committer
Ben Hutchings
<ben@decadent.org.uk>
Wed, 6 Mar 2013 03:24:07 +0000
(
03:24
+0000)
commit
210561ffd72d00eccf12c0131b8024d5436bae95
upstream.
We already have the quirk entry for the mobile platform, but also
reports on some desktop versions. So be paranoid and set it
everywhere.
References: http://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg33138.html
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: "Sankaran, Rajesh" <rajesh.sankaran@intel.com>
Reported-and-tested-by: Mihai Moldovan <ionic@ionic.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
drivers/iommu/intel-iommu.c
patch
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diff --git
a/drivers/iommu/intel-iommu.c
b/drivers/iommu/intel-iommu.c
index
dffdca8
..
f44a067
100644
(file)
--- a/
drivers/iommu/intel-iommu.c
+++ b/
drivers/iommu/intel-iommu.c
@@
-4140,13
+4140,19
@@
static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
{
/*
* Mobile 4 Series Chipset neglects to set RWBF capability,
{
/*
* Mobile 4 Series Chipset neglects to set RWBF capability,
- * but needs it
:
+ * but needs it
. Same seems to hold for the desktop versions.
*/
printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
rwbf_quirk = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
*/
printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
rwbf_quirk = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
#define GGC 0x52
#define GGC_MEMORY_SIZE_MASK (0xf << 8)
#define GGC 0x52
#define GGC_MEMORY_SIZE_MASK (0xf << 8)