pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin
to provide a reference clock to a ULPI USB PHY. This reference clock must
run at 24MHz, and the cdev2 output has no additional dividers.
Remove board-paz00.c's now-duplicate initialization of this clock.
Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
{ "uarta", "pll_p", 216000000, true },
{ "uartc", "pll_p", 216000000, true },
{ "uarta", "pll_p", 216000000, true },
{ "uartc", "pll_p", 216000000, true },
- { "pll_p_out4", "pll_p", 24000000, true },
{ "usbd", "clk_m", 12000000, false },
{ "usb2", "clk_m", 12000000, false },
{ "usb3", "clk_m", 12000000, false },
{ "usbd", "clk_m", 12000000, false },
{ "usb2", "clk_m", 12000000, false },
{ "usb3", "clk_m", 12000000, false },
{ "pll_p_out1", "pll_p", 28800000, true },
{ "pll_p_out2", "pll_p", 48000000, true },
{ "pll_p_out3", "pll_p", 72000000, true },
{ "pll_p_out1", "pll_p", 28800000, true },
{ "pll_p_out2", "pll_p", 48000000, true },
{ "pll_p_out3", "pll_p", 72000000, true },
- { "pll_p_out4", "pll_p", 108000000, true },
+ { "pll_p_out4", "pll_p", 24000000, true },
{ "pll_c", "clk_m", 600000000, true },
{ "pll_c_out1", "pll_c", 120000000, true },
{ "sclk", "pll_c_out1", 120000000, true },
{ "pll_c", "clk_m", 600000000, true },
{ "pll_c_out1", "pll_c", 120000000, true },
{ "sclk", "pll_c_out1", 120000000, true },