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(parent: 6bd13ee) | patch
ARM: zynq: Wire SPL configuration for cse nor/nand targets
authorMichal Simek <michal.simek@xilinx.com>
Thu, 29 Nov 2018 09:31:02 +0000 (10:31 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Thu, 29 Nov 2018 09:31:02 +0000 (10:31 +0100)
commitfdba86972f23cab99710e19a04f36f170d1870e0
treef3d40f8eb70814b549f5d445fb1f602d8d9e9744tree | snapshot
parent6bd13ee94ecf0e3124efdd51758df21db8100083commit | diff
ARM: zynq: Wire SPL configuration for cse nor/nand targets

These symlinks are here only for testing purpose where SPL is used
for soc configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
board/xilinx/zynq/zynq-cse-nand [new symlink] blob
board/xilinx/zynq/zynq-cse-nor [new symlink] blob
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