arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr
authorStefan Roese <sr@denx.de>
Mon, 19 Jan 2015 10:33:40 +0000 (11:33 +0100)
committerLuka Perkov <luka.perkov@sartura.hr>
Fri, 6 Feb 2015 16:25:03 +0000 (17:25 +0100)
commitf8d25d7466142c1d4ebf879e2a83a9cfc19559cb
treea825659225817a9adf8c74d0ac604278fa7a0df4
parent2e19cc316f38c56e3bbc127491bc8722c1b0386c
arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr

This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the AXP boot image. Not linked with the main U-Boot. With this code
addition and the following serdes/PHY setup code, the Armada-XP support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion. Hopefully other MVEBU SoC's will follow here.

Support for some SoC's has been removed in this version. This is:

MV_MSYS:
The code referred to by the MV_MSYS define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.

MV88F68XX (A38x):
The code referred to by the MV88F68XX define (A38x) is currently unused.
And its partial and not sufficient for this device in this stage.
So lets remove it to make the code clearer and increase the readability.

MV88F66XX (ALP):
The code referred to by the MV88F66XX define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.

MV88F78X60_Z1:
The code referred to by the MV88F78X60_Z1 define is currently unused. As the
Z1 revision of the AXP is not supported in mainline anymore.
So lets remove it to make the code clearer and increase the readability.

Remove support for Z1 & A0 AXP revisions (steppings). The current stepping
is B0 and this is the only one that is actively supported in this code
version.

Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and
on a custom fixed DDR configuration board (maxbcm).

Note:
This code has undergone many hours of coding-style cleanup and refactoring.
It still is not checkpatch clean though, I'm afraid. As the factoring of the
code has so many levels of indentation that many lines are longer than 80
chars. This might be some task to tackly later on.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
21 files changed:
drivers/ddr/mvebu/Makefile [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_axp.h [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_axp_config.h [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_axp_mc_static.h [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_axp_training_static.h [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_axp_vars.h [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_dfs.c [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_dqs.c [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_hw_training.c [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_hw_training.h [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_init.c [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_init.h [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_patterns_64bit.h [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_pbs.c [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_read_leveling.c [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_sdram.c [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_spd.c [new file with mode: 0644]
drivers/ddr/mvebu/ddr3_write_leveling.c [new file with mode: 0644]
drivers/ddr/mvebu/xor.c [new file with mode: 0644]
drivers/ddr/mvebu/xor.h [new file with mode: 0644]
drivers/ddr/mvebu/xor_regs.h [new file with mode: 0644]