x86: Align skb w/ start of cacheline on newer core 2/Xeon Arch
authorAlexander Duyck <alexander.h.duyck@intel.com>
Tue, 29 Jun 2010 18:38:00 +0000 (18:38 +0000)
committerDavid S. Miller <davem@davemloft.net>
Wed, 30 Jun 2010 21:34:09 +0000 (14:34 -0700)
commitea812ca1b06113597adcd8e70c0f84a413d97544
treee5846a631aefbcdec0a6542962e1780849fee97c
parentcb836a977f71f76ccbb1ff35b9c113ace96377e9
x86: Align skb w/ start of cacheline on newer core 2/Xeon Arch

x86 architectures can handle unaligned accesses in hardware, and it has
been shown that unaligned DMA accesses can be expensive on Nehalem
architectures.  As such we should overwrite NET_IP_ALIGN to resolve
this issue.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
arch/x86/include/asm/system.h