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arch: arm: socfpga: Configure USB3 System Manager registers
authorNaresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Wed, 24 Sep 2025 07:49:11 +0000 (00:49 -0700)
committerTien Fong Chee <tien.fong.chee@intel.com>
Tue, 30 Sep 2025 06:45:37 +0000 (14:45 +0800)
commitda57acb4c396cfc978c0652fec9dfb17a4f67ad8
treeb7ab218286786f6f97078e0f3dfa533e1b151d45tree | snapshot
parent060ed1bbbe0fd1a8583d09d7766cf3f194b23edccommit | diff
arch: arm: socfpga: Configure USB3 System Manager registers

For successful reset staggering pulse operation, reset pulse
override bit is set. Port overcurrent bit 1, which in reality
reflects PIPE power present signal is set to avoid giving
false information of Vbus status to HPS controller.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arch/arm/mach-socfpga/include/mach/system_manager_soc64.h diff | blob | history
arch/arm/mach-socfpga/system_manager_soc64.c diff | blob | history
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