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powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001
authorTimur Tabi <timur@freescale.com>
Mon, 18 Apr 2011 22:16:00 +0000 (17:16 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Fri, 29 Apr 2011 03:09:23 +0000 (22:09 -0500)
commitd90fdba6ca0b08c77cced6e914609e3696dd5909
tree6065ad540c9aeb234869d430e9b2d0ba7a4d9a1etree | snapshot
parentf68d3063491442ca5d871d3019a9d3f195873ed7commit | diff
powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001

Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1
are swapped.

Erratum SERDES-A001 says that if bank two is kept disabled and after bank
three is enabled, then the PLL for bank three won't lock properly.  The
work-around is to enable and then disable bank two after bank three is
enabled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c diff | blob | history
arch/powerpc/include/asm/config_mpc85xx.h diff | blob | history
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