Documentation: dt: add bindings for keystone pll control controller
authorIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
Fri, 23 May 2014 20:32:39 +0000 (16:32 -0400)
committerSantosh Shilimkar <santosh.shilimkar@ti.com>
Tue, 27 May 2014 13:46:39 +0000 (09:46 -0400)
commitd30982b93a79aafa688e7df1f6948ad28bb94e89
treef68de375a50253492b06181cbd27f6bec600d65e
parentcaee0055337ab96a5af844fba6e72d518d7287dd
Documentation: dt: add bindings for keystone pll control controller

The main pll controller used to drive theC66x CorePacs, the switch fabric,
and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
the NETCP modules) requires a PLL Controller to manage the various clock
divisions, gating, and synchronization.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
[santosh.shilimkar@ti.com: Fixed the subject line]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt [new file with mode: 0644]