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ARCv2: MMUv4: cache programming model changes
authorVineet Gupta <vgupta@synopsys.com>
Mon, 6 Apr 2015 11:53:57 +0000 (17:23 +0530)
committerVineet Gupta <vgupta@synopsys.com>
Mon, 22 Jun 2015 08:36:55 +0000 (14:06 +0530)
commitd1f317d8254413447bcd6b6adbde24a985d256c2
tree4b0ba3c3a5335e844edbf97403c12b88b04f69d5tree | snapshot
parentd7a512bfe0be3790bae8465b4cb6c1bbca03c616commit | diff
ARCv2: MMUv4: cache programming model changes

Caveats about cache flush on ARCv2 based cores

- dcache is PIPT so paddr is sufficient for cache maintenance ops (no
  need to setup PTAG reg

- icache is still VIPT but only aliasing configs need PTAG setup

So basically this is departure from MMU-v3 which always need vaddr in
line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG,
IC_PTAG respectively.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/Kconfig diff | blob | history
arch/arc/include/asm/arcregs.h diff | blob | history
arch/arc/include/asm/cache.h diff | blob | history
arch/arc/mm/cache.c diff | blob | history
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